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实验十一乒乓球游戏设计
1、实验目的
1、学习和理解乒乓球游戏的设计和工作原理
二、实验仪器PC机,操作系统为Windows2000/XP,本课程所用系统均为WindowsXP(下同),Mux+plusII设计平台,GW48系列SOPC/EDA实验开发系统
三、实验原理以发光二极管点亮状态做为球,8个并排发光管做球行进路线,每次点亮一个发光二极管,做为乒乓球运行的当前位置可以进行双打以两个按键开关作为球拍,由游戏者(甲、乙)各控制一个,按下开关表示击球甲乙双方各有一个记分牌,由一个数码管显示双方的得分球的运行速度在可预置1. 局比赛开始前,裁判按动每局开始发球开关,每次由右边乙方首先发球,乒乓球光点即出现在发球一方的球拍位置上,电路处于发球状态2. 能自动判球记分只要一方失球,对方记分牌上则自动加1分,即累计低分方为胜利3. 球拍按钮开关在球的一个来回中,只有第一次按动才起作用,若再次按动或持续按下不松开,将无作用即在击球时,只有在球的光点移至击球者一方球拍位置时,第一次按动按钮,击球才有效
四、实验步骤
1、利用MAX+plusII对附录的程序进行文本编辑输入和仿真测试;给出仿真波形最后进行引脚锁定并进行测试,硬件验证此游戏的系统功能
2、测试步骤Bain和bbin分别为左右球拍控制信号,分别由键8和键1控制clr是清0控制,由键7控制;clk是乒乓球行进速度时钟,接clock24HZ;souclk是失球发声时钟,接clock51024HZ;ballout7~0指示球路行进情况,用8个发光管担任,即D1~D8担任;countbh3~0和countbl3~0接数码管7和6,分别指示左边球手的得分的高位和低位;countah3~0和countal3~0接数码管3和2,分别指示右边球手的得分的高位和低位;lamp接数码管7的一个段,指示clock2速;speaker接蜂鸣器,指示失球提示
3、设目标器件是EP1K30TC144-3,本实验电路结构图NO.3,,将实验系统左下角多位选择多路开关的4号拨码打上
4、下载目标文件后,可用键1和8实验游戏图4-2实验电路结构图NO.5
五、问题讨论与提高
1、以11分为一局的话如何显示胜负局?附录libraryieee;useieee.std_logic_
1164.all;entitytennisisportbainbbinclrclksouclk:instd_logic;ballout:outstd_logic_vector7downto0;countahcountalcountbhcountbl:outstd_logic_vector3downto0;lampspeaker:outstd_logic;end;architecturefuloftennisiscomponentsoundportclksigen:instd_logic;sout:outstd_logic;endcomponent;componentballctrlportclrbainbbinserclkaserclkbclk:instd_logic;bdoutserveserclkballclrballen:outstd_logic;endcomponent;componentballportclkclrwayen:instd_logic;ballout:outstd_logic_vector7downto0;endcomponent;componentboardportballnetbclkserve:instd_logic;couclkserclk:outstd_logic;endcomponent;componentcou10portclkclr:instd_logic;cout:outstd_logic;qout:outstd_logic_vector3downto0;endcomponent;componentcou4portclkclr:instd_logic;cout:outstd_logic;qout:outstd_logic_vector3downto0;endcomponent;componentmwayportserveaserveb:instd_logic;way:outstd_logic;endcomponent;signalnetcouclkahcouclkalcouclkbhcouclkblcahcbh:std_logic;signalserveserclkaserclkbserclkballclrbdoutwayballen:std_logic;signalbbll:std_logic_vector7downto0;beginnet=bbll4;ballout=bbll;lamp=clk;uah:cou4portmapcouclkahclrcahcountah;ual:cou10portmapcouclkalclrcouclkahcountal;ubh:cou4portmapcouclkbhclrcbhcountbh;ubl:cou10portmapcouclkblclrcouclkbhcountbl;ubda:boardportmapbbll0netbainservecouclkalserclka;ubdb:boardportmapbbll7netbbinservecouclkblserclkb;ucpu:ballctrlportmapclrbainbbinserclkaserclkbclkbdoutserveserclkballclrballen;uway:mwayportmapserclkaserclkbway;uball:ballportmapclkballclrwayballenbbll;usound:soundportmapsouclkballenbdoutspeaker;end;libraryieee;useieee.std_logic_
1164.all;entitysoundisportclk:instd_logic;sig:instd_logic;en:instd_logic;sout:outstd_logic;endsound;architecturefulofsoundisbeginsout=clkandnotsiganden;end;libraryieee;useieee.std_logic_
1164.all;entityballctrlisportclr:instd_logic;bain:instd_logic;bbin:instd_logic;serclka:instd_logic;serclkb:instd_logic;clk:instd_logic;bdout:outstd_logic;serve:outstd_logic;serclk:outstd_logic;ballclr:outstd_logic;ballen:outstd_logic;endballctrl;architecturefulofballctrlissignalbd:std_logic;signalser:std_logic;beginbd=bainorbbin;ser=serclkaorserclkb;serclk=ser;bdout=bd;processclrclkbdbeginifclr=1thenserve=1;ballclr=1;elseifbd=1thenballclr=1;ifser=1thenballen=1;serve=0;elseballen=0;serve=1;endif;elseballclr=0;endif;endif;endprocess;end;libraryieee;useieee.std_logic_
1164.all;useieee.std_logic_unsigned.all;entityballisportclk:instd_logic;clr:instd_logic;way:instd_logic;en:instd_logic;ballout:outstd_logic_vector7downto0;endball;architecturefulofballissignallamp:std_logic_vector9downto0;beginprocessclkclrenbeginifclr=1thenlamp=1000000001;elsifen=0thenelsifclkeventandclk=1thenifway=1thenlamp9downto1=lamp8downto0;lamp0=0;elselamp8downto0=lamp9downto1;lamp9=0;endif;endif;ballout=lamp8downto1;endprocess;end;libraryieee;useieee.std_logic_
1164.all;entityboardisportball:instd_logic;net:instd_logic;bclk:instd_logic;serve:instd_logic;couclk:outstd_logic;serclk:outstd_logic;endboard;architecturefulofboardisbeginprocessbclknetbeginifnet=1thenserclk=0;couclk=0;elsifbclkeventandbclk=1thenifserve=1thenserclk=1;elseifball=1thenserclk=1;elseserclk=0;couclk=1;endif;endif;endif;endprocess;end;libraryieee;useieee.std_logic_
1164.all;useieee.std_logic_unsigned.all;entitycou10isportclkclr:instd_logic;cout:outstd_logic;qout:outstd_logic_vector3downto0;endcou10;architecturefulofcou10issignalqqout:std_logic_vector3downto0;beginprocessclrclkbeginifclr=1thenqqout=0000;cout=0;elsifclkeventandclk=1thenifqqout1000thenqqout=0000;cout=1;elseqqout=qqout+1;cout=0;endif;endif;qout=qqout;endprocess;end;libraryieee;useieee.std_logic_
1164.all;useieee.std_logic_unsigned.all;entitycou4isportclkclr:instd_logic;cout:outstd_logic;qout:outstd_logic_vector3downto0;endcou4;architecturefulofcou4issignalqqout:std_logic_vector3downto0;beginprocessclrclkbeginifclr=1thenqqout=0000;cout=0;elsifclkeventandclk=1thenifqqout0010thenqqout=0000;cout=1;elseqqout=qqout+1;cout=0;endif;endif;qout=qqout;endprocess;end;libraryieee;useieee.std_logic_
1164.all;entitymwayisportservea:instd_logic;serveb:instd_logic;way:outstd_logic;endmway;architecturefulofmwayisbeginprocessserveaservebbeginifservea=1thenway=1;elsifserveb=1thenway=0;endif;endprocess;end;管脚配置引脚名属性对应管脚引脚名属性对应管脚BainInput8bbinInput19Ballout0output20Countah0output41Ballout1output21Countah1output42Ballout2output22Countah2output65Ballout3output23Countah3output67Ballout4output26Countal0output36Ballout5output27Countal1output37Ballout6output28Countal2output38Ballout7output29Countal3output39Countbh0output87Countbl0output81Countbh1output88Countbl1output82Countbh2output89Countbl2output83Countbh3output90Countbl3output86lampoutput91clkinput54souclkinput56clrinput18speakeroutput99。