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TOC\o1-1\h\z\uTDC-GP2与MSP430F413通讯C程序1msp430x43x.h12TDC-GP2与MSP430F413通讯C程序//========================================#includemsp430x43x.h#includemath.h//#includeheat_meter.h//========================================#defineInit_GP2 0x70//初始化TDC#defineStart_Cycle 0x01//脉冲发送#defineStart_Temp 0x02//开始温度测量 #defineStart_Cal_Resonator 0x03//校准晶振时钟#defineStart_Cal_TDC 0x04//校准TDC//定义各管脚工作状态名称#definePVCCOn P4OUT|=BIT0#definePVCCOff P4OUT=0;#defineSSNEn P3OUT=~BIT0 //GP2R/Wenable#defineSSNDs P3OUT|=BIT0 //GP2R/Wdisable#defineRSTNHigh P3OUT|=BIT4#defineRSTNLow P3OUT=~BIT4#defineStartEn P1OUT|=BIT6 //GP2En_Start#defineStartDs P1OUT=~BIT6#defineStopEn P1OUT|=BIT7 //GP2En_Stop#defineStopDs P1OUT=~BIT7#defineUp P1OUT|=BIT2#defineDown P1OUT|=BIT3#defineClose P1OUT=~BIT2+BIT3//配置GP2流量测量//constunsignedcharConfigGP2
[23]={0x500x800x370x8A0x680x810x210x440x000x820xE00x320x000x830x080x330x000x840x200x340x000x700x01};constunsignedcharReadGP2STAT
[3]={0xB40x550x55};constunsignedcharReadRes0
[5]={0xB00x550x550x550x55};constunsignedcharReadRes1
[5]={0xB10x550x550x550x55};constunsignedcharReadRes2
[5]={0xB20x550x550x550x55};constunsignedcharReadRes3
[5]={0xB30x550x550x550x55};//=========================================//以下为初始化函数voidInitialPortvoid;//初始化端口//以下为内部函数定义,详细说明见函数部分//=======================================voidInitialGP2void;//初始化GP2voidOpCodeGP2unsignedcharopcode;//写1Byteop-codes到GP2voidConfigGP2unsignedlongdata;//配置GP2寄存器voidMeasureTempvoid;//温度测量voidReadGP2STvoid;//读GP2状态寄存器voidReadDataunsignedcharCountvolatileunsignedchar*pointvolatileunsignedchar*point_d;//读GP2结果寄存器数据voidFireStartvoid;//发送点火脉冲voidCalStartvoid;//校准时钟测量voidHXOnvoid;//切换校准时钟时高速晶振状态到开启voidHXOffvoid;//切换校准时钟时高速晶振状态到关闭voidNOP10void;//10_NOP机器周期延迟voidTempCalvoid;//温度校准测量//=======================================#pragmamemory=no_initunsignedlongDisplayData
[8];//0:heat1:cool2:volume3:heatKwh4:volumeL5:workTime6:LCDDate7:LCDTime#pragmamemory=defaultunsignedcharSPITxCountSPIRxCount;unsignedcharSPIMaskBuf
[5];unsignedcharRes0
[4];unsignedcharRes1
[4];unsignedcharRes2
[4];unsignedcharRes3
[4];unsignedintGP2ST;unsignedlongT1T2T3T4;unsignedlongPT1PT2;floatCorrectFactor;constfloatA=
3.862314E-3;constfloatB=-
6.531493E-7;//=======================================unionlongValue{ unsignedlonguWord; unsignedcharlByte
[4];};unionintValue{ unsignedintuInt; unsignedcharlByte
[2];};//=======================================voidmainvoid{ InitialPort; _EINT; SPIRxCount=0; Delay50000; _NOP; PVCCOn; InitialGP2;//初始化GP2 while1 { //HXOn; //Delay5000; CalStart; //时钟校准 //HXOff; //MeasureTemp; //_NOP; //TempCal; //DisplayPT1; //LCDRAM
[3]|=0x80; //StopWTD; //AdjustLCD; //RunLCD; Close; Up; FireStart; Close; Down; LPM0; ReadGP2ST; ReadData5unsignedchar*ReadRes0unsignedchar*Res0; ReadData5unsignedchar*ReadRes1unsignedchar*Res1; ReadData5unsignedchar*ReadRes2unsignedchar*Res2; ReadData5unsignedchar*ReadRes3unsignedchar*Res3; _NOP; StopWTD; LPM3; /*InitialGP2; Close; Down; FireStart; Close; Up; //LPM0; StopWTD; LPM3; */ }} //=======================================//端口初始化voidInitialPortvoid{ WDTCTL=WDTPW+WDTHOLD; //StopWDT //FLL_CTL0=XCAP14PF; //setloadcapacitancefor32kxtal //SCFQCTL=SCFQ_4M; //LCDCTL=LCDON+LCD4MUX+LCDP1; //STKLCD4MuxS0-S19 //BTCTL=BTFRFQ0; //STKLCDfreq P5SEL=0xFC; //CommonandRxxallselected P4DIR|=BIT0; //PVCC P1SEL|=BIT5; P1DIR|=BIT2+BIT3+BIT5+BIT6+BIT7; //P
1.2SW2P
1.3SW1 //P
1.
532.768kHzOutputasGP2Clock //P
1.6asGP2En_StartP
1.7asGP2En_Stop P2DIR|=BIT2+BIT3; P2IE|=BIT7; P2IES|=BIT7; TACTL=TASSEL_1+MC_2+TACLR; //ACLKcontinousmode ME1|=USPIE0; //EnableUSART0SPImode UCTL0|=CHAR+SYNC+MM; //8-bitSPIMaster**SWRST** UTCTL0|=/*CKPH+*/SSEL1+SSEL0+STC; //SMCLK3-pinmode UBR00=0x02; //UCLK/2 UBR10=0x00; //0 UMCTL0=0x00; //nomodulation UCTL0=~SWRST; //InitalizeUSARTstatemachine IE1|=URXIE0; //Receiveinterruptenable P3SEL|=0x0E; //P
3.1-3SPIoptionselect P3DIR|=BIT0+BIT4; //P
3.0outputdirection TBCTL=TBSSEL_1+ID_2+TBCLR; //SetupTimer_B TBCCR1=16384; TBCCTL1=CCIE; TBCTL|=MC_2;}//========================================//GP2寄存器配置voidInitialGP2void{ unsignedchari=0; SSNDs; _NOP; RSTNHigh; _NOP; RSTNLow; _NOP; RSTNHigh; StartEn; //开启start_en StopEn;//开启stop_en OpCodeGP20x50; //GP2复位 _NOP; ConfigGP20x80338468;//内部不分频,fire脉冲频率为1MHz,发送3个fire脉冲对于4MHz时钟校准是基于8个周期的32K时钟,高速时钟持续工作,温度测量应用高速时钟128us周期时间2次热身测量,4个温度测量端口(2个温度传感器,一个测冷水,一个测热水)TDC自动校准,选择测量范围2 _NOP; ConfigGP20x81214400;//ALU计算第一个stop-start _NOP; ConfigGP20x82E01900;//启动所有GP2中断源,设置第一个stop的使能窗口,在50us后允许接受第一个stop脉冲 _NOP; ConfigGP20x83081A00;//设置第2个stop的使能窗口,在51us后允许接受第二个stop脉冲,256us后未接到stop信号溢出 _NOP; ConfigGP20x84201A80;//设置第3个stop德使能窗口,在52us后允许接受第三个stop脉冲 _NOP; ConfigGP20x85000000; _NOP;}//-----------------------------------voidFireStartvoid{ OpCodeGP20x70; //Init //Delay4000; _NOP; OpCodeGP20x01; //StartCycle //ReadGP2ST; _NOP;}//-----------------------------------voidMeasureTempvoid{ unsignedchari; unionlongValuevardata; Delay500; OpCodeGP2Start_Temp; Delay500; //waitformeasurementfinish ReadGP2ST; ifGP2ST0x1E00 { T1=0; T2=0; T3=0; T4=0; return; } ReadData5unsignedchar*ReadRes0unsignedchar*Res0; ReadData5unsignedchar*ReadRes1unsignedchar*Res1; ReadData5unsignedchar*ReadRes2unsignedchar*Res2; ReadData5unsignedchar*ReadRes3unsignedchar*Res3; _NOP; fori=0;i4;i++ { vardata.lByte[i]=Res0[i]; } T1=vardata.uWord; fori=0;i4;i++ { vardata.lByte[i]=Res1[i]; } T2=vardata.uWord; fori=0;i4;i++ { vardata.lByte[i]=Res2[i]; } T3=vardata.uWord; fori=0;i4;i++ { vardata.lByte[i]=Res3[i]; } T4=vardata.uWord; _NOP; }//-----------------------------------voidCalStartvoid{ unsignedchari; unsignedintHigh16Low16; floatbuf; unionlongValuevardata; unionintValuevarint; OpCodeGP20x03; LPM0; ReadData5unsignedchar*ReadRes0unsignedchar*Res0; fori=0;i4;i++ { vardata.lByte[i]=Res0[i]; } varint.lByte
[0]=vardata.lByte
[0]; varint.lByte
[1]=vardata.lByte
[1]; Low16=varint.uInt; varint.lByte
[0]=vardata.lByte
[2]; varint.lByte
[1]=vardata.lByte
[3]; High16=varint.uInt; buf=floatLow16; CorrectFactor=buf/65536+High16; CorrectFactor*=1000; DisplayCorrectFactor; LCDRAM
[4]|=0x80; AdjustLCD; RunLCD;}//===================================voidHXOnvoid{ ConfigGP20x80324668;}//===================================voidHXOffvoid{ ConfigGP20x80324E68;} //===================================voidOpCodeGP2unsignedcharopcode//senda1ByteopcodetotheTDC-GP2{ SSNDs; _NOP; SSNEn; _NOP; IE1=~URXIE0; //Receiveinterruptdisable TXBUF0=opcode; while!IFG1UTXIFG0; NOP10; //LPM0; SSNDs; IFG1=~URXIFG0; IE1|=URXIE0; //Receiveinterruptenable }//========================================voidConfigGP2unsignedlongdata //配置TDC-GP2寄存器{ unsignedchari; unionlongValuevardata; vardata.uWord=data; SSNDs; _NOP; SSNEn; _NOP; //TXBUF0=vardata.lByte
[3]; fori=0;i4;i++ { //LPM0; TXBUF0=vardata.lByte[3-i]; LPM0; } SSNDs;}//========================================voidReadGP2STvoid{ unsignedchari=0; SSNDs; SSNEn; SPIRxCount=0; fori=0;i3;i++ { TXBUF0=ReadGP2STAT[i]; LPM0; } //NOP10; SSNDs; GP2ST=SPIMaskBuf
[1]; GP2ST=8; GP2ST|=SPIMaskBuf
[2];}//========================================voidReadDataunsignedcharCountvolatileunsignedchar*pointvolatileunsignedchar*point_d{ unsignedchari; SSNDs; SSNEn; SPIRxCount=0; fori=0;iCount;i++ { TXBUF0=*point+i; LPM0; } //NOP10; SSNDs; fori=1;i5;i++ { *point_d+i-1=SPIMaskBuf[5-i]; }}//========================================voidTempCalvoid{ floattemptemp1tempref; temp1=T4; tempref=T1; temp=temp1/tempref; PT1=temp*100000;}//========================================interrupt[UART0RX_VECTOR]voids_receivevoid{ whileIFG1UTXIFG0==0; ifSPIRxCount5 { SPIMaskBuf[SPIRxCount]=RXBUF0; SPIRxCount++; //SSNDs; } else { SPIRxCount=0; } LPM0_EXIT;}//========================================voidNOP10void{ _NOP; _NOP; _NOP; _NOP; _NOP; _NOP; _NOP; _NOP; _NOP; _NOP;}//=========================================interrupt[TIMERB1_VECTOR]voidtimerb1_intvoid{ TBCCR1+=16384; TBCCTL1=~CCIFG; //ClearWTD; _BIC_SR_IRQLPM3_bits; }//===========================================interrupt[PORT2_VECTOR]voidGP2_intvoid{ P2IFG=0; LPM0_EXIT;}msp430x43x.h/**********************************************************************StandardregisterandbitdefinitionsfortheTexasInstruments*MSP430microcontroller.**ThisfilesupportsassemblerandC/EC++developmentfor*MSP430x43xdevices.**Version
2.0*********************************************************************/#ifndef__msp430x43x#define__msp430x43x#if__TID__80x7F!=0x2b/*0x2b=43dec*/#errorMSP430X43X.HfileforusewithICC430/A430only#endif#ifdef__IAR_SYSTEMS_ICC__#includein
430.h#pragmalanguage=extended#defineDEFCnameaddress__no_initvolatileunsignedcharname@address;#defineDEFWnameaddress__no_initvolatileunsignedshortname@address;#endif/*__IAR_SYSTEMS_ICC__*/#ifdef__IAR_SYSTEMS_ASM__#defineDEFCnameaddresssfrbname=address;#defineDEFWnameaddresssfrwname=address;#endif/*__IAR_SYSTEMS_ASM__*/#ifdef__cplusplus#defineREAD_ONLY#else#defineREAD_ONLYconst#endif/*************************************************************STANDARDBITS************************************************************/#defineBIT00x0001#defineBIT10x0002#defineBIT20x0004#defineBIT30x0008#defineBIT40x0010#defineBIT50x0020#defineBIT60x0040#defineBIT70x0080#defineBIT80x0100#defineBIT90x0200#defineBITA0x0400#defineBITB0x0800#defineBITC0x1000#defineBITD0x2000#defineBITE0x4000#defineBITF0x8000/*************************************************************STATUSREGISTERBITS************************************************************/#defineC0x0001#defineZ0x0002#defineN0x0004#defineV0x0100#defineGIE0x0008#defineCPUOFF0x0010#defineOSCOFF0x0020#defineSCG00x0040#defineSCG10x0080/*LowPowerModescodedwithBits4-7inSR*/#ifndef__IAR_SYSTEMS_ICC/*Begin#definesforassembler*/#defineLPM0CPUOFF#defineLPM1SCG0+CPUOFF#defineLPM2SCG1+CPUOFF#defineLPM3SCG1+SCG0+CPUOFF#defineLPM4SCG1+SCG0+OSCOFF+CPUOFF/*End#definesforassembler*/#else/*Begin#definesforC*/#defineLPM0_bitsCPUOFF#defineLPM1_bitsSCG0+CPUOFF#defineLPM2_bitsSCG1+CPUOFF#defineLPM3_bitsSCG1+SCG0+CPUOFF#defineLPM4_bitsSCG1+SCG0+OSCOFF+CPUOFF#defineLPM0_BIS_SRLPM0_bits/*EnterLowPowerMode0*/#defineLPM0_EXIT_BIC_SR_IRQLPM0_bits/*ExitLowPowerMode0*/#defineLPM1_BIS_SRLPM1_bits/*EnterLowPowerMode1*/#defineLPM1_EXIT_BIC_SR_IRQLPM1_bits/*ExitLowPowerMode1*/#defineLPM2_BIS_SRLPM2_bits/*EnterLowPowerMode2*/#defineLPM2_EXIT_BIC_SR_IRQLPM2_bits/*ExitLowPowerMode2*/#defineLPM3_BIS_SRLPM3_bits/*EnterLowPowerMode3*/#defineLPM3_EXIT_BIC_SR_IRQLPM3_bits/*ExitLowPowerMode3*/#defineLPM4_BIS_SRLPM4_bits/*EnterLowPowerMode4*/#defineLPM4_EXIT_BIC_SR_IRQLPM4_bits/*ExitLowPowerMode4*/#endif/*End#definesforC*//*************************************************************PERIPHERALFILEMAP************************************************************//*************************************************************SPECIALFUNCTIONREGISTERADDRESSES+CONTROLBITS************************************************************/#defineIE1_0x0000/*InterruptEnable1*/DEFCIE1IE1_#defineU0IE_IE1_/*UART0InterruptEnableRegister*/DEFCU0IEU0IE_#defineWDTIE0x01#defineOFIE0x02#defineNMIIE0x10#defineACCVIE0x20#defineURXIE00x40#defineUTXIE00x80#defineIFG1_0x0002/*InterruptFlag1*/DEFCIFG1IFG1_#defineU0IFG_IFG1_/*UART0InterruptFlagRegister*/DEFCU0IFGU0IFG_#defineWDTIFG0x01#defineOFIFG0x02#defineNMIIFG0x10#defineURXIFG00x40#defineUTXIFG00x80#defineME1_0x0004/*ModuleEnable1*/DEFCME1ME1_#defineU0ME_ME1_/*UART0ModuleEnableRegister*/DEFCU0MEU0ME_#defineURXE00x40#defineUSPIE00x40#defineUTXE00x80#defineIE2_0x0001/*InterruptEnable2*/DEFCIE2IE2_#defineBTIE0x80#defineIFG2_0x0003/*InterruptFlag2*/DEFCIFG2IFG2_#defineBTIFG0x80/*************************************************************WATCHDOGTIMER************************************************************/#defineWDTCTL_0x0120/*WatchdogTimerControl*/DEFWWDTCTLWDTCTL_/*ThebitnameshavebeenprefixedwithWDT*/#defineWDTIS00x0001#defineWDTIS10x0002#defineWDTSSEL0x0004#defineWDTCNTCL0x0008#defineWDTTMSEL0x0010#defineWDTNMI0x0020#defineWDTNMIES0x0040#defineWDTHOLD0x0080#defineWDTPW0x5A00/*WDT-intervaltimes[1ms]codedwithBits0-2*//*WDTisclockedbyfMCLKassumed1MHz*/#defineWDT_MDLY_32WDTPW+WDTTMSEL+WDTCNTCL/*32msintervaldefault*/#defineWDT_MDLY_8WDTPW+WDTTMSEL+WDTCNTCL+WDTIS0/*8ms*/#defineWDT_MDLY_0_5WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1/*
0.5ms*/#defineWDT_MDLY_0_064WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1+WDTIS0/*
0.064ms*//*WDTisclockedbyfACLKassumed32KHz*/#defineWDT_ADLY_1000WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL/*1000ms*/#defineWDT_ADLY_250WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS0/*250ms*/#defineWDT_ADLY_16WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1/*16ms*/#defineWDT_ADLY_1_9WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0/*
1.9ms*//*Watchdogmode-resetafterexpiredtime*//*WDTisclockedbyfMCLKassumed1MHz*/#defineWDT_MRST_32WDTPW+WDTCNTCL/*32msintervaldefault*/#defineWDT_MRST_8WDTPW+WDTCNTCL+WDTIS0/*8ms*/#defineWDT_MRST_0_5WDTPW+WDTCNTCL+WDTIS1/*
0.5ms*/#defineWDT_MRST_0_064WDTPW+WDTCNTCL+WDTIS1+WDTIS0/*
0.064ms*//*WDTisclockedbyfACLKassumed32KHz*/#defineWDT_ARST_1000WDTPW+WDTCNTCL+WDTSSEL/*1000ms*/#defineWDT_ARST_250WDTPW+WDTCNTCL+WDTSSEL+WDTIS0/*250ms*/#defineWDT_ARST_16WDTPW+WDTCNTCL+WDTSSEL+WDTIS1/*16ms*/#defineWDT_ARST_1_9WDTPW+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0/*
1.9ms*//*INTERRUPTCONTROL*//*ThesetwobitsaredefinedintheSpecialFunctionRegisters*//*#defineWDTIE0x01*//*#defineWDTIFG0x01*//*************************************************************DIGITALI/OPort1/2************************************************************/#defineP1IN_0x0020/*Port1Input*/READ_ONLYDEFCP1INP1IN_#defineP1OUT_0x0021/*Port1Output*/DEFCP1OUTP1OUT_#defineP1DIR_0x0022/*Port1Direction*/DEFCP1DIRP1DIR_#defineP1IFG_0x0023/*Port1InterruptFlag*/DEFCP1IFGP1IFG_#defineP1IES_0x0024/*Port1InterruptEdgeSelect*/DEFCP1IESP1IES_#defineP1IE_0x0025/*Port1InterruptEnable*/DEFCP1IEP1IE_#defineP1SEL_0x0026/*Port1Selection*/DEFCP1SELP1SEL_#defineP2IN_0x0028/*Port2Input*/READ_ONLYDEFCP2INP2IN_#defineP2OUT_0x0029/*Port2Output*/DEFCP2OUTP2OUT_#defineP2DIR_0x002A/*Port2Direction*/DEFCP2DIRP2DIR_#defineP2IFG_0x002B/*Port2InterruptFlag*/DEFCP2IFGP2IFG_#defineP2IES_0x002C/*Port2InterruptEdgeSelect*/DEFCP2IESP2IES_#defineP2IE_0x002D/*Port2InterruptEnable*/DEFCP2IEP2IE_#defineP2SEL_0x002E/*Port2Selection*/DEFCP2SELP2SEL_/*************************************************************DIGITALI/OPort3/4************************************************************/#defineP3IN_0x0018/*Port3Input*/READ_ONLYDEFCP3INP3IN_#defineP3OUT_0x0019/*Port3Output*/DEFCP3OUTP3OUT_#defineP3DIR_0x001A/*Port3Direction*/DEFCP3DIRP3DIR_#defineP3SEL_0x001B/*Port3Selection*/DEFCP3SELP3SEL_#defineP4IN_0x001C/*Port4Input*/READ_ONLYDEFCP4INP4IN_#defineP4OUT_0x001D/*Port4Output*/DEFCP4OUTP4OUT_#defineP4DIR_0x001E/*Port4Direction*/DEFCP4DIRP4DIR_#defineP4SEL_0x001F/*Port4Selection*/DEFCP4SELP4SEL_/*************************************************************DIGITALI/OPort5/6************************************************************/#defineP5IN_0x0030/*Port5Input*/READ_ONLYDEFCP5INP5IN_#defineP5OUT_0x0031/*Port5Output*/DEFCP5OUTP5OUT_#defineP5DIR_0x0032/*Port5Direction*/DEFCP5DIRP5DIR_#defineP5SEL_0x0033/*Port5Selection*/DEFCP5SELP5SEL_#defineP6IN_0x0034/*Port6Input*/READ_ONLYDEFCP6INP6IN_#defineP6OUT_0x0035/*Port6Output*/DEFCP6OUTP6OUT_#defineP6DIR_0x0036/*Port6Direction*/DEFCP6DIRP6DIR_#defineP6SEL_0x0037/*Port6Selection*/DEFCP6SELP6SEL_/*************************************************************BASICTIMER************************************************************/#defineBTCTL_0x0040/*BasicTimerControl*/DEFCBTCTLBTCTL_/*ThebitnameshavebeenprefixedwithBT*/#defineBTIP00x01#defineBTIP10x02#defineBTIP20x04#defineBTFRFQ00x08#defineBTFRFQ10x10#defineBTDIV0x20/*fCLK2ACLK:256*//*#defineBTRESET0x40*//*incorrect:BTisresetandBTIFGisresetifthisbitisset*/#defineBTHOLD0x40/*BT1isheldifthisbitisset*/#defineBTSSEL0x80/*fBTfMCLKmainclock*/#defineBTCNT1_0x0046/*BasicTimerCount1*/DEFCBTCNT1BTCNT1_#defineBTCNT2_0x0047/*BasicTimerCount2*/DEFCBTCNT2BTCNT2_/*FrequencyoftheBTCNT2codedwithBit5and7inBTCTL*/#defineBT_fCLK2_ACLK0x00#defineBT_fCLK2_ACLK_DIV256BTDIV#defineBT_fCLK2_MCLKBTSSEL/*InterruptintervaltimefINTcodedwithBits0-2inBTCTL*/#defineBT_fCLK2_DIV20x00/*fINTfCLK2:2default*/#defineBT_fCLK2_DIV4BTIP0/*fINTfCLK2:4*/#defineBT_fCLK2_DIV8BTIP1/*fINTfCLK2:8*/#defineBT_fCLK2_DIV16BTIP1+BTIP0/*fINTfCLK2:16*/#defineBT_fCLK2_DIV32BTIP2/*fINTfCLK2:32*/#defineBT_fCLK2_DIV64BTIP2+BTIP0/*fINTfCLK2:64*/#defineBT_fCLK2_DIV128BTIP2+BTIP1/*fINTfCLK2:128*/#defineBT_fCLK2_DIV256BTIP2+BTIP1+BTIP0/*fINTfCLK2:256*//*FrequencyofLCDcodedwithBits3-4*/#defineBT_fLCD_DIV320x00/*fLCDfACLK:32default*/#defineBT_fLCD_DIV64BTFRFQ0/*fLCDfACLK:64*/#defineBT_fLCD_DIV128BTFRFQ1/*fLCDfACLK:128*/#defineBT_fLCD_DIV256BTFRFQ1+BTFRFQ0/*fLCDfACLK:256*//*LCDfrequencyvalueswithfBTfACLK*/#defineBT_fLCD_1K0x00/*fACLK:32default*/#defineBT_fLCD_512BTFRFQ0/*fACLK:64*/#defineBT_fLCD_256BTFRFQ1/*fACLK:128*/#defineBT_fLCD_128BTFRFQ1+BTFRFQ0/*fACLK:256*//*LCDfrequencyvalueswithfBTfMCLK*/#defineBT_fLCD_31KBTSSEL/*fMCLK:32*/#defineBT_fLCD_15_5KBTSSEL+BTFRFQ0/*fMCLK:64*/#defineBT_fLCD_7_8KBTSSEL+BTFRFQ1+BTFRFQ0/*fMCLK:256*//*withassumedvluesoffACLK32KHzfMCLK1MHz*//*fBTfACLKisthoughtforlongerintervaltimes*/#defineBT_ADLY_0_0640x00/*
0.064msintervaldefault*/#defineBT_ADLY_0_125BTIP0/*
0.125ms*/#defineBT_ADLY_0_25BTIP1/*
0.25ms*/#defineBT_ADLY_0_5BTIP1+BTIP0/*
0.5ms*/#defineBT_ADLY_1BTIP2/*1ms*/#defineBT_ADLY_2BTIP2+BTIP0/*2ms*/#defineBT_ADLY_4BTIP2+BTIP1/*4ms*/#defineBT_ADLY_8BTIP2+BTIP1+BTIP0/*8ms*/#defineBT_ADLY_16BTDIV/*16ms*/#defineBT_ADLY_32BTDIV+BTIP0/*32ms*/#defineBT_ADLY_64BTDIV+BTIP1/*64ms*/#defineBT_ADLY_125BTDIV+BTIP1+BTIP0/*125ms*/#defineBT_ADLY_250BTDIV+BTIP2/*250ms*/#defineBT_ADLY_500BTDIV+BTIP2+BTIP0/*500ms*/#defineBT_ADLY_1000BTDIV+BTIP2+BTIP1/*1000ms*/#defineBT_ADLY_2000BTDIV+BTIP2+BTIP1+BTIP0/*2000ms*//*fCLK2fMCLK1MHzisthoughtforshortintervaltimes*//*thetimingforshortintervalsismoreprecisethanACLK*//*NOTE*//*BesurethattheSCFQCTL-Registerissetto01FhsothatfMCLK1MHz*//*Toolowintervaltimeresultsininterruptstoofrequentfortheprocessortohandle!*/#defineBT_MDLY_0_002BTSSEL/*
0.002msinterval***intervaltimes*/#defineBT_MDLY_0_004BTSSEL+BTIP0/*
0.004ms***tooshortfor*/#defineBT_MDLY_0_008BTSSEL+BTIP1/*
0.008ms***interrupt*/#defineBT_MDLY_0_016BTSSEL+BTIP1+BTIP0/*
0.016ms***handling*/#defineBT_MDLY_0_032BTSSEL+BTIP2/*
0.032ms*/#defineBT_MDLY_0_064BTSSEL+BTIP2+BTIP0/*
0.064ms*/#defineBT_MDLY_0_125BTSSEL+BTIP2+BTIP1/*
0.125ms*/#defineBT_MDLY_0_25BTSSEL+BTIP2+BTIP1+BTIP0/*
0.25ms*//*Reset/HoldcodedwithBits6-7inBT1CTL*//*thisisforBT*/#defineBTRESET_CNT1BTRESET/*BTCNT1isresetwhileBTRESETisset*/#defineBTRESET_CNT1_2BTRESET+BTDIV/*BTCNT
1.AND.BTCNT2areresetwhile~isset*//*thisisforBT1*/#defineBTHOLD_CNT1BTHOLD/*BTCNT1isheldwhileBTHOLDisset*/#defineBTHOLD_CNT1_2BTHOLD+BTDIV/*BT1CNT
1.AND.BT1CNT2areheldwhile~isset*//*INTERRUPTCONTROLBITS*//*#defineBTIE0x80*//*#defineBTIFG0x80*//*************************************************************SYSTEMCLOCKFLL+************************************************************/#defineSCFI0_0x0050/*SystemClockFrequencyIntegrator0*/DEFCSCFI0SCFI0_#defineFN_20x04/*fDCOCLK2*fNominal*/#defineFN_30x08/*fDCOCLK3*fNominal*/#defineFN_40x10/*fDCOCLK
4.5*fNominal*/#defineFN_80x20/*fDCOCLK10*fNominal*/#defineFLLD00x40/*LoopDividerBit:0*/#defineFLLD10x80/*LoopDividerBit:1*/#defineFLLD_10x00/*MultiplySelectedLoopFreq.By1*/#defineFLLD_20x40/*MultiplySelectedLoopFreq.By2*/#defineFLLD_40x80/*MultiplySelectedLoopFreq.By4*/#defineFLLD_80xC0/*MultiplySelectedLoopFreq.By8*/#defineSCFI1_0x0051/*SystemClockFrequencyIntegrator1*/DEFCSCFI1SCFI1_#defineSCFQCTL_0x0052/*SystemClockFrequencyControl*/DEFCSCFQCTLSCFQCTL_/*SystemclockfrequencyvaluesfMCLKcodedwithBits0-6inSCFQCTL*//*#defineSCFQ_32K0x00fMCLK1*fACLKonlyarangefrom*/#defineSCFQ_64K0x01/*fMCLK2*fACLK1+1to127+1ispossible*/#defineSCFQ_128K0x03/*fMCLK4*fACLK*/#defineSCFQ_256K0x07/*fMCLK8*fACLK*/#defineSCFQ_512K0x0F/*fMCLK16*fACLK*/#defineSCFQ_1M0x1F/*fMCLK32*fACLK*/#defineSCFQ_2M0x3F/*fMCLK64*fACLK*/#defineSCFQ_4M0x7F/*fMCLK128*fACLK*/#defineSCFQ_M0x80/*ModulationDisable*/#defineFLL_CTL0_0x0053/*FLL+Control0*/DEFCFLL_CTL0FLL_CTL0_#defineDCOF0x01/*DCOFaultFlag*/#defineLFOF0x02/*LowFrequencyOscillatorFaultFlag*/#defineXT1OF0x04/*HighFrequencyOscillator1FaultFlag*/#defineXT2OF0x08/*HighFrequencyOscillator2FaultFlag*/#defineOSCCAP00x10/*XIN/XOUTCap0*/#defineOSCCAP10x20/*XIN/XOUTCap1*/#defineXTS_FLL0x40/*1:Selectshigh-freq.oscillator*/#defineDCOPLUS0x80/*DCO+Enable*/#defineXCAP0PF0x00/*XINCap=XOUTCap=0pf*/#defineXCAP10PF0x10/*XINCap=XOUTCap=10pf*/#defineXCAP14PF0x20/*XINCap=XOUTCap=14pf*/#defineXCAP18PF0x30/*XINCap=XOUTCap=18pf*/#defineFLL_CTL1_0x0054/*FLL+Control1*/DEFCFLL_CTL1FLL_CTL1_#defineFLL_DIV00x00/*FLL+DividePx.x/ACLK0*/#defineFLL_DIV10x01/*FLL+DividePx.x/ACLK1*/#defineSELS0x04/*PeripheralModuleClockSource0:DCO1:XT2*/#defineSELM00x08/*MCLKSourceSelect0*/#defineSELM10x10/*MCLKSourceSelect1*/#defineXT2OFF0x20/*HighFrequencyOscillator2XT2disable*/#defineFLL_DIV_10x00/*FLL+DividePx.x/ACLKBy1*/#defineFLL_DIV_20x01/*FLL+DividePx.x/ACLKBy2*/#defineFLL_DIV_40x02/*FLL+DividePx.x/ACLKBy4*/#defineFLL_DIV_80x03/*FLL+DividePx.x/ACLKBy8*/#defineSELM_DCO0x00/*SelectDCOforCPUMCLK*/#defineSELM_XT20x10/*SelectXT2forCPUMCLK*/#defineSELM_A0x18/*SelectAfromLFXT1forCPUMCLK*/#defineSMCLKOFF0x40/*PeripheralModuleClockSMCLKdisable*//*INTERRUPTCONTROLBITS*//*ThesetwobitsaredefinedintheSpecialFunctionRegisters*//*#defineOFIFG0x02*//*#defineOFIE0x02*//*************************************************************Brown-OutSupplyVoltageSupervisionSVS************************************************************/#defineSVSCTL_0x0056/*SVSControl*/DEFCSVSCTLSVSCTL_#defineSVSFG0x01#defineSVSOP0x02#defineSVSON0x04#definePORON0x08#defineVLDOFF0x00#defineVLDON0x10#defineVLD_1_8V0x10/*************************************************************LCD************************************************************/#defineLCDCTL_0x0090/*LCDControl*/DEFCLCDCTLLCDCTL_/*thenamesofthemodebitsaredifferentfromthespec*/#defineLCDON0x01#defineLCDLOWR0x02#defineLCDSON0x04#defineLCDMX00x08#defineLCDMX10x10#defineLCDP00x20#defineLCDP10x40#defineLCDP20x80/*DisplaymodescodedwithBits2-4*/#defineLCDSTATICLCDSON#defineLCD2MUXLCDMX0+LCDSON#defineLCD3MUXLCDMX1+LCDSON#defineLCD4MUXLCDMX1+LCDMX0+LCDSON/*GroupselectcodewithBits5-7Seg.linesDig.output*/#defineLCDSG00x00/*---------PortOnlydefault*/#defineLCDSG0_1LCDP0/*S0-S15seeDatasheet*/#defineLCDSG0_2LCDP1/*S0-S19seeDatasheet*/#defineLCDSG0_3LCDP1+LCDP0/*S0-S23seeDatasheet*/#defineLCDSG0_4LCDP2/*S0-S27seeDatasheet*/#defineLCDSG0_5LCDP2+LCDP0/*S0-S31seeDatasheet*/#defineLCDSG0_6LCDP2+LCDP1/*S0-S35seeDatasheet*/#defineLCDSG0_7LCDP2+LCDP1+LCDP0/*S0-S39seeDatasheet*//*NOTE:YOUCANONLYUSETHESORGDECLARATIONSFORACOMMAND*//*MOV#LCDSG0_3+LCDOG2_7LCDCTLACTUALYMEANSMOV#LCDP1LCDCTL!*/#defineLCDOG1_70x00/*---------PortOnlydefault*/#defineLCDOG2_7LCDP0/*S0-S15seeDatasheet*/#defineLCDOG3_7LCDP1/*S0-S19seeDatasheet*/#defineLCDOG4_7LCDP1+LCDP0/*S0-S23seeDatasheet*/#defineLCDOG5_7LCDP2/*S0-S27seeDatasheet*/#defineLCDOG6_7LCDP2+LCDP0/*S0-S31seeDatasheet*/#defineLCDOG7LCDP2+LCDP1/*S0-S35seeDatasheet*/#defineLCDOGOFFLCDP2+LCDP1+LCDP0/*S0-S39seeDatasheet*/#defineLCDMEM_0x0091/*LCDMemory*/#ifndef__IAR_SYSTEMS_ICC#defineLCDMEMLCDMEM_/*LCDMemoryforassembler*/#else#defineLCDMEMchar*LCDMEM_/*LCDMemoryforC*/#endif#defineLCDM1_LCDMEM_/*LCDMemory1*/DEFCLCDM1LCDM1_#defineLCDM2_0x0092/*LCDMemory2*/DEFCLCDM2LCDM2_#defineLCDM3_0x0093/*LCDMemory3*/DEFCLCDM3LCDM3_#defineLCDM4_0x0094/*LCDMemory4*/DEFCLCDM4LCDM4_#defineLCDM5_0x0095/*LCDMemory5*/DEFCLCDM5LCDM5_#defineLCDM6_0x0096/*LCDMemory6*/DEFCLCDM6LCDM6_#defineLCDM7_0x0097/*LCDMemory7*/DEFCLCDM7LCDM7_#defineLCDM8_0x0098/*LCDMemory8*/DEFCLCDM8LCDM8_#defineLCDM9_0x0099/*LCDMemory9*/DEFCLCDM9LCDM9_#defineLCDM10_0x009A/*LCDMemory10*/DEFCLCDM10LCDM10_#defineLCDM11_0x009B/*LCDMemory11*/DEFCLCDM11LCDM11_#defineLCDM12_0x009C/*LCDMemory12*/DEFCLCDM12LCDM12_#defineLCDM13_0x009D/*LCDMemory13*/DEFCLCDM13LCDM13_#defineLCDM14_0x009E/*LCDMemory14*/DEFCLCDM14LCDM14_#defineLCDM15_0x009F/*LCDMemory15*/DEFCLCDM15LCDM15_#defineLCDM16_0x00A0/*LCDMemory16*/DEFCLCDM16LCDM16_#defineLCDM17_0x00A1/*LCDMemory17*/DEFCLCDM17LCDM17_#defineLCDM18_0x00A2/*LCDMemory18*/DEFCLCDM18LCDM18_#defineLCDM19_0x00A3/*LCDMemory19*/DEFCLCDM19LCDM19_#defineLCDM20_0x00A4/*LCDMemory20*/DEFCLCDM20LCDM20_#defineLCDMA_LCDM10_/*LCDMemoryA*/DEFCLCDMALCDMA_#defineLCDMB_LCDM11_/*LCDMemoryB*/DEFCLCDMBLCDMB_#defineLCDMC_LCDM12_/*LCDMemoryC*/DEFCLCDMCLCDMC_#defineLCDMD_LCDM13_/*LCDMemoryD*/DEFCLCDMDLCDMD_#defineLCDME_LCDM14_/*LCDMemoryE*/DEFCLCDMELCDME_#defineLCDMF_LCDM15_/*LCDMemoryF*/DEFCLCDMFLCDMF_/*************************************************************USART************************************************************/#definePENA0x80/*UCTL*/#definePEV0x40#defineSPB0x20/*todistinguishfromstackpointerSP*/#defineCHAR0x10#defineLISTEN0x08#defineSYNC0x04#defineMM0x02#defineSWRST0x01#defineCKPH0x80/*UTCTL*/#defineCKPL0x40#defineSSEL10x20#defineSSEL00x10#defineURXSE0x08#defineTXWAKE0x04#defineSTC0x02#defineTXEPT0x01#defineFE0x80/*URCTL*/#definePE0x40#defineOE0x20#defineBRK0x10#defineURXEIE0x08#defineURXWIE0x04#defineRXWAKE0x02#defineRXERR0x01/*************************************************************USART0************************************************************/#defineU0CTL_0x0070/*USART0Control*/DEFCU0CTLU0CTL_#defineU0TCTL_0x0071/*USART0TransmitControl*/DEFCU0TCTLU0TCTL_#defineU0RCTL_0x0072/*USART0ReceiveControl*/DEFCU0RCTLU0RCTL_#defineU0MCTL_0x0073/*USART0ModulationControl*/DEFCU0MCTLU0MCTL_#defineU0BR0_0x0074/*USART0BaudRate0*/DEFCU0BR0U0BR0_#defineU0BR1_0x0075/*USART0BaudRate1*/DEFCU0BR1U0BR1_#defineU0RXBUF_0x0076/*USART0ReceiveBuffer*/READ_ONLYDEFCU0RXBUFU0RXBUF_#defineU0TXBUF_0x0077/*USART0TransmitBuffer*/DEFCU0TXBUFU0TXBUF_/*Alternateregisternames*/#defineUCTL0_U0CTL_/*USART0Control*/DEFCUCTL0UCTL0_#defineUTCTL0_U0TCTL_/*USART0TransmitControl*/DEFCUTCTL0UTCTL0_#defineURCTL0_U0RCTL_/*USART0ReceiveControl*/DEFCURCTL0URCTL0_#defineUMCTL0_U0MCTL_/*USART0ModulationControl*/DEFCUMCTL0UMCTL0_#defineUBR00_U0BR0_/*USART0BaudRate0*/DEFCUBR00UBR00_#defineUBR10_U0BR1_/*USART0BaudRate1*/DEFCUBR10UBR10_#defineRXBUF0_U0RXBUF_/*USART0ReceiveBuffer*/READ_ONLYDEFCRXBUF0RXBUF0_#defineTXBUF0_U0TXBUF_/*USART0TransmitBuffer*/DEFCTXBUF0TXBUF0_#defineUCTL_0_U0CTL_/*USART0Control*/DEFCUCTL_0UCTL_0_#defineUTCTL_0_U0TCTL_/*USART0TransmitControl*/DEFCUTCTL_0UTCTL_0_#defineURCTL_0_U0RCTL_/*USART0ReceiveControl*/DEFCURCTL_0URCTL_0_#defineUMCTL_0_U0MCTL_/*USART0ModulationControl*/DEFCUMCTL_0UMCTL_0_#defineUBR0_0_U0BR0_/*USART0BaudRate0*/DEFCUBR0_0UBR0_0_#defineUBR1_0_U0BR1_/*USART0BaudRate1*/DEFCUBR1_0UBR1_0_#defineRXBUF_0_U0RXBUF_/*USART0ReceiveBuffer*/READ_ONLYDEFCRXBUF_0RXBUF_0_#defineTXBUF_0_U0TXBUF_/*USART0TransmitBuffer*/DEFCTXBUF_0TXBUF_0_/*************************************************************TimerA************************************************************/#defineTAIV_0x012E/*TimerAInterruptVectorWord*/READ_ONLYDEFWTAIVTAIV_#defineTACTL_0x0160/*TimerAControl*/DEFWTACTLTACTL_#defineTACCTL0_0x0162/*TimerACapture/CompareControl0*/DEFWTACCTL0TACCTL0_#defineTACCTL1_0x0164/*TimerACapture/CompareControl1*/DEFWTACCTL1TACCTL1_#defineTACCTL2_0x0166/*TimerACapture/CompareControl2*/DEFWTACCTL2TACCTL2_#defineTAR_0x0170/*TimerA*/DEFWTARTAR_#defineTACCR0_0x0172/*TimerACapture/Compare0*/DEFWTACCR0TACCR0_#defineTACCR1_0x0174/*TimerACapture/Compare1*/DEFWTACCR1TACCR1_#defineTACCR2_0x0176/*TimerACapture/Compare2*/DEFWTACCR2TACCR2_/*Alternateregisternames*/#defineCCTL0_TACCTL0_/*TimerACapture/CompareControl0*/DEFWCCTL0CCTL0_#defineCCTL1_TACCTL1_/*TimerACapture/CompareControl1*/DEFWCCTL1CCTL1_#defineCCTL2_TACCTL2_/*TimerACapture/CompareControl2*/DEFWCCTL2CCTL2_#defineCCR0_TACCR0_/*TimerACapture/Compare0*/DEFWCCR0CCR0_#defineCCR1_TACCR1_/*TimerACapture/Compare1*/DEFWCCR1CCR1_#defineCCR2_TACCR2_/*TimerACapture/Compare2*/DEFWCCR2CCR2_#defineTASSEL20x0400/*unused*//*todistinguishfromUSARTSSELx*/#defineTASSEL10x0200/*TimerAclocksourceselect0*/#defineTASSEL00x0100/*TimerAclocksourceselect1*/#defineID10x0080/*TimerAclockinputdevider1*/#defineID00x0040/*TimerAclockinputdevider0*/#defineMC10x0020/*TimerAmodecontrol1*/#defineMC00x0010/*TimerAmodecontrol0*/#defineTACLR0x0004/*TimerAcounterclear*/#defineTAIE0x0002/*TimerAcounterinterruptenable*/#defineTAIFG0x0001/*TimerAcounterinterruptflag*/#defineMC_00*0x10/*TimerAmodecontrol:0-Stop*/#defineMC_11*0x10/*TimerAmodecontrol:1-UptoCCR0*/#defineMC_22*0x10/*TimerAmodecontrol:2-Continousup*/#defineMC_33*0x10/*TimerAmodecontrol:3-Up/Down*/#defineID_00*0x40/*TimerAinputdivider:0-/1*/#defineID_11*0x40/*TimerAinputdivider:1-/2*/#defineID_22*0x40/*TimerAinputdivider:2-/4*/#defineID_33*0x40/*TimerAinputdivider:3-/8*/#defineTASSEL_00*0x100/*TimerAclocksourceselect:0-TACLK*/#defineTASSEL_11*0x100/*TimerAclocksourceselect:1-ACLK*/#defineTASSEL_22*0x100/*TimerAclocksourceselect:2-SMCLK*/#defineTASSEL_33*0x100/*TimerAclocksourceselect:3-INCLK*/#defineCM10x8000/*Capturemode1*/#defineCM00x4000/*Capturemode0*/#defineCCIS10x2000/*Captureinputselect1*/#defineCCIS00x1000/*Captureinputselect0*/#defineSCS0x0800/*Capturesychronize*/#defineSCCI0x0400/*Latchedcapturesignalread*/#defineCAP0x0100/*Capturemode:1/Comparemode:0*/#defineOUTMOD20x0080/*Outputmode2*/#defineOUTMOD10x0040/*Outputmode1*/#defineOUTMOD00x0020/*Outputmode0*/#defineCCIE0x0010/*Capture/compareinterruptenable*/#defineCCI0x0008/*Captureinputsignalread*/#defineOUT0x0004/*PWMOutputsignalifoutputmode0*/#defineCOV0x0002/*Capture/compareoverflowflag*/#defineCCIFG0x0001/*Capture/compareinterruptflag*/#defineOUTMOD_00*0x20/*PWMoutputmode:0-outputonly*/#defineOUTMOD_11*0x20/*PWMoutputmode:1-set*/#defineOUTMOD_22*0x20/*PWMoutputmode:2-PWMtoggle/reset*/#defineOUTMOD_33*0x20/*PWMoutputmode:3-PWMset/reset*/#defineOUTMOD_44*0x20/*PWMoutputmode:4-toggle*/#defineOUTMOD_55*0x20/*PWMoutputmode:5-Reset*/#defineOUTMOD_66*0x20/*PWMoutputmode:6-PWMtoggle/set*/#defineOUTMOD_77*0x20/*PWMoutputmode:7-PWMreset/set*/#defineCCIS_00*0x1000/*Captureinputselect:0-CCIxA*/#defineCCIS_11*0x1000/*Captureinputselect:1-CCIxB*/#defineCCIS_22*0x1000/*Captureinputselect:2-GND*/#defineCCIS_33*0x1000/*Captureinputselect:3-Vcc*/#defineCM_00*0x4000u/*Capturemode:0-disabled*/#defineCM_11*0x4000u/*Capturemode:1-pos.edge*/#defineCM_22*0x4000u/*Capturemode:1-neg.edge*/#defineCM_33*0x4000u/*Capturemode:1-bothedges*//*************************************************************TimerB************************************************************/#defineTBIV_0x011E/*TimerBInterruptVectorWord*/READ_ONLYDEFWTBIVTBIV_#defineTBCTL_0x0180/*TimerBControl*/DEFWTBCTLTBCTL_#defineTBCCTL0_0x0182/*TimerBCapture/CompareControl0*/DEFWTBCCTL0TBCCTL0_#defineTBCCTL1_0x0184/*TimerBCapture/CompareControl1*/DEFWTBCCTL1TBCCTL1_#defineTBCCTL2_0x0186/*TimerBCapture/CompareControl2*/DEFWTBCCTL2TBCCTL2_#defineTBR_0x0190/*TimerB*/DEFWTBRTBR_#defineTBCCR0_0x0192/*TimerBCapture/Compare0*/DEFWTBCCR0TBCCR0_#defineTBCCR1_0x0194/*TimerBCapture/Compare1*/DEFWTBCCR1TBCCR1_#defineTBCCR2_0x0196/*TimerBCapture/Compare2*/DEFWTBCCR2TBCCR2_#defineSHR10x4000/*TimerBComparelatchloadgroup1*/#defineSHR00x2000/*TimerBComparelatchloadgroup0*/#defineTBCLGRP10x4000/*TimerBComparelatchloadgroup1*/#defineTBCLGRP00x2000/*TimerBComparelatchloadgroup0*/#defineCNTL10x1000/*Counterlenght1*/#defineCNTL00x0800/*Counterlenght0*/#defineTBSSEL20x0400/*unused*/#defineTBSSEL10x0200/*Clocksource1*/#defineTBSSEL00x0100/*Clocksource0*/#defineTBCLR0x0004/*TimerBcounterclear*/#defineTBIE0x0002/*TimerBinterruptenable*/#defineTBIFG0x0001/*TimerBinterruptflag*/#defineTBSSEL_00*0x0100/*ClockSource:TBCLK*/#defineTBSSEL_11*0x0100/*ClockSource:ACLK*/#defineTBSSEL_22*0x0100/*ClockSource:SMCLK*/#defineTBSSEL_33*0x0100/*ClockSource:INCLK*/#defineCNTL_00*0x0800/*Counterlenght:16bit*/#defineCNTL_11*0x0800/*Counterlenght:12bit*/#defineCNTL_22*0x0800/*Counterlenght:10bit*/#defineCNTL_33*0x0800/*Counterlenght:8bit*/#defineSHR_00*0x2000/*TimerBGroup:0-individually*/#defineSHR_11*0x2000/*TimerBGroup:1-3groups1-23-45-6*/#defineSHR_22*0x2000/*TimerBGroup:2-2groups1-34-6*/#defineSHR_33*0x2000/*TimerBGroup:3-1groupall*/#defineTBCLGRP_00*0x2000/*TimerBGroup:0-individually*/#defineTBCLGRP_11*0x2000/*TimerBGroup:1-3groups1-23-45-6*/#defineTBCLGRP_22*0x2000/*TimerBGroup:2-2groups1-34-6*/#defineTBCLGRP_33*0x2000/*TimerBGroup:3-1groupall*//*AdditionalTimerBControlRegisterbitsaredefinedinTimerA*/#defineSLSHR10x0400/*Comparelatchloadsource1*/#defineSLSHR00x0200/*Comparelatchloadsource0*/#defineCLLD10x0400/*Comparelatchloadsource1*/#defineCLLD00x0200/*Comparelatchloadsource0*/#defineSLSHR_00*0x0200/*Comparelatchloadsourec:0-immediate*/#defineSLSHR_11*0x0200/*Comparelatchloadsourec:1-TBRcountsto0*/#defineSLSHR_22*0x0200/*Comparelatchloadsourec:2-up/down*/#defineSLSHR_33*0x0200/*Comparelatchloadsourec:3-TBRcountstoTBCTL0*/#defineCLLD_00*0x0200/*Comparelatchloadsourec:0-immediate*/#defineCLLD_11*0x0200/*Comparelatchloadsourec:1-TBRcountsto0*/#defineCLLD_22*0x0200/*Comparelatchloadsourec:2-up/down*/#defineCLLD_33*0x0200/*Comparelatchloadsourec:3-TBRcountstoTBCTL0*//**************************************************************FlashMemory*************************************************************/#defineFCTL1_0x0128/*FLASHControl1*/DEFWFCTL1FCTL1_#defineFCTL2_0x012A/*FLASHControl2*/DEFWFCTL2FCTL2_#defineFCTL3_0x012C/*FLASHControl3*/DEFWFCTL3FCTL3_#defineFRKEY0x9600/*Flashkeyreturnedbyread*/#defineFWKEY0xA500/*Flashkeyforwrite*/#defineFXKEY0x3300/*forusewithXORinstruction*/#defineERASE0x0002/*EnablebitforFlashsegmenterase*/#defineMERAS0x0004/*EnablebitforFlashmasserase*/#defineWRT0x0040/*EnablebitforFlashwrite*/#defineBLKWRT0x0080/*EnablebitforFlashsegmentwrite*/#defineSEGWRT0x0080/*olddefinition*//*EnablebitforFlashsegmentwrite*/#defineFN00x0001/*DevideFlashclockby1to64usingFN0toFN5accordingto:*/#defineFN10x0002/*32*FN5+16*FN4+8*FN3+4*FN2+2*FN1+FN0+1*/#defineFN20x0004#defineFN30x0008#defineFN40x0010#defineFN50x0020#defineFSSEL00x0040/*Flashclockselect0*//*todistinguishfromUSARTSSELx*/#defineFSSEL10x0080/*Flashclockselect1*/#defineFSSEL_00x0000/*Flashclockselect:0-ACLK*/#defineFSSEL_10x0040/*Flashclockselect:1-MCLK*/#defineFSSEL_20x0080/*Flashclockselect:2-SMCLK*/#defineFSSEL_30x00C0/*Flashclockselect:3-SMCLK*/#defineBUSY0x0001/*Flashbusy:1*/#defineKEYV0x0002/*FlashKeyviolationflag*/#defineACCVIFG0x0004/*FlashAccessviolationflag*/#defineWAIT0x0008/*Waitflagforsegmentwrite*/#defineLOCK0x0010/*Lockbit:1-Flashislockedreadonly*/#defineEMEX0x0020/*FlashEmergencyExit*//*************************************************************ComparatorA************************************************************/#defineCACTL1_0x0059/*ComparatorAControl1*/DEFCCACTL1CACTL1_#defineCACTL2_0x005A/*ComparatorAControl2*/DEFCCACTL2CACTL2_#defineCAPD_0x005B/*ComparatorAPortDisable*/DEFCCAPDCAPD_#defineCAIFG0x01/*Comp.AInterruptFlag*/#defineCAIE0x02/*Comp.AInterruptEnable*/#defineCAIES0x04/*Comp.AInt.EdgeSelect:0:rising/1:falling*/#defineCAON0x08/*Comp.Aenable*/#defineCAREF00x10/*Comp.AInternalReferenceSelect0*/#defineCAREF10x20/*Comp.AInternalReferenceSelect1*/#defineCARSEL0x40/*Comp.AInternalReferenceEnable*/#defineCAEX0x80/*Comp.AExchangeInputs*/#defineCAREF_00x00/*Comp.AInt.Ref.Select0:Off*/#defineCAREF_10x10/*Comp.AInt.Ref.Select1:
0.25*Vcc*/#defineCAREF_20x20/*Comp.AInt.Ref.Select2:
0.5*Vcc*/#defineCAREF_30x30/*Comp.AInt.Ref.Select3:Vt*/#defineCAOUT0x01/*Comp.AOutput*/#defineCAF0x02/*Comp.AEnableOutputFilter*/#defineP2CA00x04/*Comp.AConnectExternalSignaltoCA0:1*/#defineP2CA10x08/*Comp.AConnectExternalSignaltoCA1:1*/#defineCACTL240x10#defineCACTL250x20#defineCACTL260x40#defineCACTL270x80#defineCAPD00x01/*Comp.ADisableInputBufferofPortRegister.0*/#defineCAPD10x02/*Comp.ADisableInputBufferofPortRegister.1*/#defineCAPD20x04/*Comp.ADisableInputBufferofPortRegister.2*/#defineCAPD30x08/*Comp.ADisableInputBufferofPortRegister.3*/#defineCAPD40x10/*Comp.ADisableInputBufferofPortRegister.4*/#defineCAPD50x20/*Comp.ADisableInputBufferofPortRegister.5*/#defineCAPD60x40/*Comp.ADisableInputBufferofPortRegister.6*/#defineCAPD70x80/*Comp.ADisableInputBufferofPortRegister.7*//*************************************************************ADC12************************************************************/#defineADC12CTL0_0x01A0/*ADC12Control0*/DEFWADC12CTL0ADC12CTL0_#defineADC12CTL1_0x01A2/*ADC12Control1*/DEFWADC12CTL1ADC12CTL1_#defineADC12IFG_0x01A4/*ADC12InterruptFlag*/DEFWADC12IFGADC12IFG_#defineADC12IE_0x01A6/*ADC12InterruptEnable*/DEFWADC12IEADC12IE_#defineADC12IV_0x01A8/*ADC12InterruptVectorWord*/DEFWADC12IVADC12IV_#defineADC12MEM_0x0140/*ADC12ConversionMemory*/#ifndef__IAR_SYSTEMS_ICC#defineADC12MEMADC12MEM_/*ADC12ConversionMemoryforassembler*/#else#defineADC12MEMint*ADC12MEM_/*ADC12ConversionMemoryforC*/#endif#defineADC12MEM0_ADC12MEM_/*ADC12ConversionMemory0*/DEFWADC12MEM0ADC12MEM0_#defineADC12MEM1_0x0142/*ADC12ConversionMemory1*/DEFWADC12MEM1ADC12MEM1_#defineADC12MEM2_0x0144/*ADC12ConversionMemory2*/DEFWADC12MEM2ADC12MEM2_#defineADC12MEM3_0x0146/*ADC12ConversionMemory3*/DEFWADC12MEM3ADC12MEM3_#defineADC12MEM4_0x0148/*ADC12ConversionMemory4*/DEFWADC12MEM4ADC12MEM4_#defineADC12MEM5_0x014A/*ADC12ConversionMemory5*/DEFWADC12MEM5ADC12MEM5_#defineADC12MEM6_0x014C/*ADC12ConversionMemory6*/DEFWADC12MEM6ADC12MEM6_#defineADC12MEM7_0x014E/*ADC12ConversionMemory7*/DEFWADC12MEM7ADC12MEM7_#defineADC12MEM8_0x0150/*ADC12ConversionMemory8*/DEFWADC12MEM8ADC12MEM8_#defineADC12MEM9_0x0152/*ADC12ConversionMemory9*/DEFWADC12MEM9ADC12MEM9_#defineADC12MEM10_0x0154/*ADC12ConversionMemory10*/DEFWADC12MEM10ADC12MEM10_#defineADC12MEM11_0x0156/*ADC12ConversionMemory11*/DEFWADC12MEM11ADC12MEM11_#defineADC12MEM12_0x0158/*ADC12ConversionMemory12*/DEFWADC12MEM12ADC12MEM12_#defineADC12MEM13_0x015A/*ADC12ConversionMemory13*/DEFWADC12MEM13ADC12MEM13_#defineADC12MEM14_0x015C/*ADC12ConversionMemory14*/DEFWADC12MEM14ADC12MEM14_#defineADC12MEM15_0x015E/*ADC12ConversionMemory15*/DEFWADC12MEM15ADC12MEM15_#defineADC12MCTL_0x0080/*ADC12MemoryControl*/#ifndef__IAR_SYSTEMS_ICC#defineADC12MCTLADC12MCTL_/*ADC12MemoryControlforassembler*/#else#defineADC12MCTLchar*ADC12MCTL_/*ADC12MemoryControlforC*/#endif#defineADC12MCTL0_ADC12MCTL_/*ADC12MemoryControl0*/DEFCADC12MCTL0ADC12MCTL0_#defineADC12MCTL1_0x0081/*ADC12MemoryControl1*/DEFCADC12MCTL1ADC12MCTL1_#defineADC12MCTL2_0x0082/*ADC12MemoryControl2*/DEFCADC12MCTL2ADC12MCTL2_#defineADC12MCTL3_0x0083/*ADC12MemoryControl3*/DEFCADC12MCTL3ADC12MCTL3_#defineADC12MCTL4_0x0084/*ADC12MemoryControl4*/DEFCADC12MCTL4ADC12MCTL4_#defineADC12MCTL5_0x0085/*ADC12MemoryControl5*/DEFCADC12MCTL5ADC12MCTL5_#defineADC12MCTL6_0x0086/*ADC12MemoryControl6*/DEFCADC12MCTL6ADC12MCTL6_#defineADC12MCTL7_0x0087/*ADC12MemoryControl7*/DEFCADC12MCTL7ADC12MCTL7_#defineADC12MCTL8_0x0088/*ADC12MemoryControl8*/DEFCADC12MCTL8ADC12MCTL8_#defineADC12MCTL9_0x0089/*ADC12MemoryControl9*/DEFCADC12MCTL9ADC12MCTL9_#defineADC12MCTL10_0x008A/*ADC12MemoryControl10*/DEFCADC12MCTL10ADC12MCTL10_#defineADC12MCTL11_0x008B/*ADC12MemoryControl11*/DEFCADC12MCTL11ADC12MCTL11_#defineADC12MCTL12_0x008C/*ADC12MemoryControl12*/DEFCADC12MCTL12ADC12MCTL12_#defineADC12MCTL13_0x008D/*ADC12MemoryControl13*/DEFCADC12MCTL13ADC12MCTL13_#defineADC12MCTL14_0x008E/*ADC12MemoryControl14*/DEFCADC12MCTL14ADC12MCTL14_#defineADC12MCTL15_0x008F/*ADC12MemoryControl15*/DEFCADC12MCTL15ADC12MCTL15_#defineADC12SC0x001/*ADC12CTL0*/#defineENC0x002#defineADC12TOVIE0x004#defineADC12OVIE0x008#defineADC12ON0x010#defineREFON0x020#defineREF2_5V0x040#defineMSH0x080#defineMSC0x080#defineSHT0_00*0x100#defineSHT0_11*0x100#defineSHT0_22*0x100#defineSHT0_33*0x100#defineSHT0_44*0x100#defineSHT0_55*0x100#defineSHT0_66*0x100#defineSHT0_77*0x100#defineSHT0_88*0x100#defineSHT0_99*0x100#defineSHT0_1010*0x100#defineSHT0_1111*0x100#defineSHT0_1212*0x100#defineSHT0_1313*0x100#defineSHT0_1414*0x100#defineSHT0_1515*0x100#defineSHT1_00*0x1000#defineSHT1_11*0x1000#defineSHT1_22*0x1000#defineSHT1_33*0x1000#defineSHT1_44*0x1000#defineSHT1_55*0x1000#defineSHT1_66*0x1000#defineSHT1_77*0x1000#defineSHT1_88*0x1000#defineSHT1_99*0x1000#defineSHT1_1010*0x1000#defineSHT1_1111*0x1000#defineSHT1_1212*0x1000#defineSHT1_1313*0x1000#defineSHT1_1414*0x1000#defineSHT1_1515*0x1000#defineADC12BUSY0x0001/*ADC12CTL1*/#defineCONSEQ_00*2#defineCONSEQ_11*2#defineCONSEQ_22*2#defineCONSEQ_33*2#defineADC12SSEL_00*8#defineADC12SSEL_11*8#defineADC12SSEL_22*8#defineADC12SSEL_33*8#defineADC12DIV_00*0x20#defineADC12DIV_11*0x20#defineADC12DIV_22*0x20#defineADC12DIV_33*0x20#defineADC12DIV_44*0x20#defineADC12DIV_55*0x20#defineADC12DIV_66*0x20#defineADC12DIV_77*0x20#defineISSH0x0100#defineSHP0x0200#defineSHS_00*0x400#defineSHS_11*0x400#defineSHS_22*0x400#defineSHS_33*0x400#defineCSTARTADD_00*0x1000#defineCSTARTADD_11*0x1000#defineCSTARTADD_22*0x1000#defineCSTARTADD_33*0x1000#defineCSTARTADD_44*0x1000#defineCSTARTADD_55*0x1000#defineCSTARTADD_66*0x1000#defineCSTARTADD_77*0x1000#defineCSTARTADD_88*0x1000#defineCSTARTADD_99*0x1000#defineCSTARTADD_1010*0x1000#defineCSTARTADD_1111*0x1000#defineCSTARTADD_1212*0x1000#defineCSTARTADD_1313*0x1000#defineCSTARTADD_1414*0x1000#defineCSTARTADD_1515*0x1000#defineINCH_00/*ADC12MCTLx*/#defineINCH_11#defineINCH_22#defineINCH_33#defineINCH_44#defineINCH_55#defineINCH_66#defineINCH_77#defineINCH_88#defineINCH_99#defineINCH_1010#defineINCH_1111#defineINCH_1212#defineINCH_1313#defineINCH_1414#defineINCH_1515#defineSREF_00*0x10#defineSREF_11*0x10#defineSREF_22*0x10#defineSREF_33*0x10#defineSREF_44*0x10#defineSREF_55*0x10#defineSREF_66*0x10#defineSREF_77*0x10#defineEOS0x80/*************************************************************InterruptVectorsoffsetfrom0xFFE0************************************************************/#defineBASICTIMER_VECTOR0*2/*0xFFE0BasicTimer*/#definePORT2_VECTOR1*2/*0xFFE2Port2*/#definePORT1_VECTOR4*2/*0xFFE8Port1*/#defineTIMERA1_VECTOR5*2/*0xFFEATimerACC1-2TA*/#defineTIMERA0_VECTOR6*2/*0xFFECTimerACC0*/#defineADC_VECTOR7*2/*0xFFEEADC*/#defineUSART0TX_VECTOR8*2/*0xFFF0USART0Transmit*/#defineUSART0RX_VECTOR9*2/*0xFFF2USART0Receive*/#defineWDT_VECTOR10*2/*0xFFF4WatchdogTimer*/#defineCOMPARATORA_VECTOR11*2/*0xFFF6ComparatorA*/#defineTIMERB1_VECTOR12*2/*0xFFF8TimerB1-2*/#defineTIMERB0_VECTOR13*2/*0xFFFATimerB0*/#defineNMI_VECTOR14*2/*0xFFFCNon-maskable*/#defineRESET_VECTOR15*2/*0xFFFEReset[HighestPriority]*/#defineUART0TX_VECTORUSART0TX_VECTOR#defineUART0RX_VECTORUSART0RX_VECTOR/*************************************************************EndofModule************************************************************/#pragmalanguage=default#endif/*#ifndef__msp430x43x*/。