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问答Pointoutdesignobjectsinthefiguresuchas:designcellreferenceportpinnetthenwriteacommandtoset5tonetADesign:topReference:ADDDFFCell:U1U2Port:ABclksumPin:ABDQNet:ABSINSet_load5[get_netsA]whydowenotchoosetooperateallourdigitalcircuitsattheselowsupplyvoltages答1)不加区分地降低电源电压虽然对减少能耗能正面影响,但它绝对会使门的延时加大2)一旦电源电压和本征电压(阈值电压)变得可比拟,DC特性对器件参数(如晶体管阈值)的变化就变得越来越敏感3)降低电源电压意味着减少信号摆幅虽然这通常可以帮助减少系统的内部噪声(如串扰引起的噪声),但它也使设计对并不减少的外部噪声源更加敏感)问道题
1.CMOS静态电路中,上拉网络为什么用PMOS下拉网络为什么用NMOS管
1.什么是亚阈值电流,当减少VT时,VGS=0时的亚阈值电流是增加还是减少?
1.什么是速度饱和效应
1.CMOS电压越低,功耗就越少?是不是数字电路电源电压越低越好,为什么?
1.如何减少门的传输延迟?P
2031.CMOS电路中有哪些类型的功耗?
1.什么是衬垫偏置效应
1.gate-to-channelcapacitanceCGC包括哪些部分VirSim有哪几类窗口3-
6.GiventhedatainTable
0.1forashortchannelNMOStransistorwithVDSAT=
0.6Vandk′=100µA/V2calculateVT0γλ2|φf|andW/L:解答:对于短沟道器件在选择公式的时候,首先要确定工作区域,表格中的所有VDS均大于VDSAT,所以不可能工作在线性区域如果工作在饱和区域则VT应该满足:VGS-VTVDSAT2-VT
0.
61.4VT这是不可能的,所以可以假设所有的数据都是工作在速度饱和区域所以由12所以123是在速度饱和区由23由241297/1146=[(2-Vt0)x
0.6-o.62/2]/[2-Vtx
0.6-
0.62/2]Vt=
0.587V由25Vt=
0.691V这两个值都满足Vt
1.4所以表中的数据都是工作的速度饱和状态由45和可以计算出和得到W/L=
1.53-7GivenTable
0.2thegoalistoderivetheimportantdeviceparametersfromthesedatapoints.Asthemeasuredtransistorisprocessedinadeep-submcirontechnologythe‘unifiedmodel’holds.FromthematerialconstantswealsocoulddeterminethatthesaturationvoltageVDSATequals-1V.Youmayalsoassumethat-2ΦF=-
0.6V.NOTE:TheparametervaluesonTable
3.3doNOTholdforthisproblem.a.IsthemeasuredtransistoraPMOSoranNMOSdeviceExplainyouranswer.b.DeterminethevalueofVT
0.c.Determineγ.d.Determineλ.e.Giventheobtainedanswersdetermineforeachofthemeasurementstheoperationregionofthetransistorchoosefromcutoffresistivesaturatedandvelocitysaturated.Annotateyourfindingintheright-mostcolumnoftheabove.解答:a这是PMOS器件b比较各表中的值知道1,4为工作在速度饱和状态由14Vt0=
0.5Vc由15和上面求出的Vt0的值:1,5工作在速度饱和区域则(-
84.375)/-
72.0=[(-
2.5-Vt0)*-1-12/2]/[-
2.5-Vt*-1-12/2]求出Vt,代入下面公式求出γ=
0.538V1/2d由16,因为1,6均工作在速度饱和区域:λ=
0.05V-1e1-vel.Sat2-cutoff3-saturation4-5-6vel.Sat7-linear3-8AnNMOSdeviceispluggedintothetestconfigurationshownbelowinFigure
0.
4.TheinputVin=2V.Thecurrentsourcedrawsaconstantcurrentof50µA.Risavariableresistorthatcanassumevaluesbetween10kΩand30kΩ.TransistorM1experiencesshortchanneleffectsandhasfollowingtransistorparameters:k’=110*10-6V/A2VT=
0.4andVDSAT=
0.6V.ThetransistorhasaW/L=
2.5µ/
0.25µ.Forsimplicitybodyeffectandchannellengthmodulationcanbeneglected.i.eλ=0γ=
0..a.WhenR=10kΩfindtheoperationregionVDandVS.b.WhenR=30kΩagaindeterminetheoperationregionVDVSc.ForthecaseofR=10kΩwouldVSincreaseordecreaseifλ≠
0.Explainqualitatively解答:1当R=10kVD=VDD-IRVD=
2.5-50x10-6x104=
2.5-
0.5=2V假设器件工作在饱和区需要以后验证则=
0.3V所以VGS=
0.3+
0.4=
0.7VVS=2-
0.7=
1.3VVmin=minVGS-VtVDSATVDS=min
0.
30.
60.7=VGS-Vt所以是饱和区VD=2VVS=
1.3VsaturationoperationbVD=
2.5-30x103x50x10-6=
2.5-
1.5=1Vassumelinearop:MinVGS-VTVDSVDSAT=min1-
0.93-
0.
4.
0.070=VDSSOlinearcincreaseR=10kΩR变化,则VD必须变化以保持电流稳定,试图增加电流,而为了恒定电流值,VGS必须减小,即VS必须增加
1、
(10)P137Assumeaninverterinthegeneric
0.25mmCMOStechnologydesignedwithaPMOS/NMOSratioof
3.4andwiththeNMOStransistorminimumsizeW=
0.375mmL=
0.25mmW/L=
1.
5.VM=
1.25VpleasecomputeVILVIHNMLNMH.theprocessparametersispresentedintable1由此可以得到VILVIHNMLNMH:因为VIH=VM-VM/gVIL=VM+VDD-VM/gNMH=VDD-VIHNML=VILVIL=
1.2VVIH=
1.3VNML=NMH=
1.
25.
3、FortheinverterofFigure1andanoutputloadof3pF,atVout=
2.5VIDVsat=
0.439mAatVout=
1.25VIDvsat=
0.41mAfig1a.Calculatetplhtphlandtp.b.AretherisingandfallingdelaysequalWhyorwhynot解答tpLH=
0.69RLCL=155nsec.对于tpHL:首先计算RonforVoutat
2.5Vand
1.25V.因为Vout=
2.5VIDVsat=
0.439mA所以Ron=5695当Vout=
1.25VIDvsat=
0.41m所以Ron=
3049.这样,Vout=
2.5VandVout=
1.25V之间的平均电阻Raverage=
4.372ktpLH=
0.69RaverageCL=
9.05nsec.tp=av{tpLHtpHL}=
82.0nsecb.AretherisingandfallingdelaysequalWhyorwhynotSolutiontpLHtpHL因为RL=75k远大于有效线性电阻effectivelinearizedon-resistanceofM
1.5-5ThenextfigureshowstwoimplementationsofMOSinverters.ThefirstinverterusesonlyNMOStransistors.CalculateVOHVOLVMforeachcase.有的参数参考表1解答电路A.VOH:当M1关掉,M2的阈值是:当下面条件满足的时候,M2将关闭:所以VOUT=VOH=
1.765VVOL:假设VIN=VDD=
2.5V.我们期望VOUT为低因此我们可以假设M2工作在速度饱和区,而M1工作在线性区域.因为ID1=ID2所以VOUT=VOL=
0.263V假设成立VM:当VM=VIN=VOUT.假设两晶体管均工作在速度饱和区域我们得到下面两个方程:设ID1=ID2得到VM=
1.269V电路B.当VIN=0VNMOS关掉,PMOS打开,并把VOUT拉到VDDsoVOH=
2.
5.同样当VIN=
2.5VthePMOS关掉,NMOS把VOUT拉到地所以VOL=0V.为了计算VM VM=VIN=VOUT.假设两晶体管均工作在速度饱和区域,可以得到下面两组方程.设ID3+ID2=0可以得到rVM=
1.095V.所以假设两晶体管均工作在速度饱和区域是正确的.5-7ConsiderthecircuitinFigure
5.
5.DeviceM1isastandardNMOSdevice.DeviceM2hasallthesamepropertiesasM1exceptthatitsdevicethresholdvoltageisnegativeandhasavalueof-
0.4V.AssumethatallthecurrentequationsandinequalityequationstodeterminethemodeofoperationforthedepletiondeviceM2arethesameasaregularNMOS.AssumethattheinputINhasa0Vto
2.5Vswing.VDSAT=
0.63va.DeviceM2hasitsgateterminalconnectedtoitssourceterminal.IfVIN=0VwhatistheoutputvoltageInsteadystatewhatisthemodeofoperationofdeviceM2forthisinputb.ComputetheoutputvoltageforVIN=
2.5V.YoumayassumethatVOUTissmalltosimplifyyourcalculation.InsteadystatewhatisthemodeofoperationofdeviceM2forthisinput解答a当VIN=0V,M1则关掉.M2开,因为VGS=0VTn
2.所以没有电流通过M2M2的源漏电压等于0,故M2工作在线性区域,所以VOUT=
2.5V.Solutionb假设M1工作在线性区域,M2工作在速度饱和区域,这就意味因为Vout很小,所以可以忽略V2out/2所以可以得到因此我们的假设是合理的5-15Sizingachainofinverters.a.InordertodrivealargecapacitanceCL=20pFfromaminimumsizegatewithinputcapacitanceCi=10fFyoudecidetointroduceatwo-stagedbufferasshowninFigure,Assumethatthepropagationdelayofaminimumsizeinverteris70ps.Alsoassumethattheinputcapacitanceofagateisproportionaltoitssize.Determinethesizingofthetwoadditionalbufferstagesthatwillminimizethepropagationdelay.b.IfyoucouldaddanynumberofstagestoachievetheminimumdelayhowmanystageswouldyouinsertWhatisthepropagationdelayinthiscase解答a:当每个buffer的延迟相等的时候,可以得到最小延迟时间.此时每个buffer的尺寸系数分别为ff2解答b:最小延迟时间发生在f=e的时候,因此6-1ImplementtheequationusingcomplementaryCMOS.SizethedevicessothattheoutputresistanceisthesameasthatofaninverterwithanNMOSW/L=2andPMOSW/L=
6.Whichinputpatternswouldgivetheworstandbestequivalentpull-uporpull-downresistance解答因为最坏的上拉电阻发生在,只有一个通路存在outputnodetoVdd.如ABCDEFG=1111100and
0101110.最好的上拉电阻发生在ABCDEFG=
0000000.最坏的下拉电阻发生在,只有一个通路存在outputnodetoGND.如ABCDEFG=0000001and
0011110.最好的下拉电阻发生在ABCDEFG=
1111111.5章Assumeaninverterinthegeneric
0.25mCMOStechnologydesignedwithaPMOS/NMOSratioof
3.4andwiththeNMOStransistorminimumsizeW=
0.375mmL=
0.25mmW/L=
1.
5.PleasecomputeVILVIHNMLNMHtheprocessparametersispresentedintable1解我们首先计算在VM=
1.25V的增益所以VIL=
1.2VVIH=
1.3VNML=NMH=
1.
21.Howtodeducethatthepropagationdelayofagatep203KeepcapacitancesCLsmallIncreasetransistorsizesW/LIncreaseVDDseefigure
5.22减小CL:增加晶体管的W/L,提高VDD
2.DeterminethesizesoftheinvertersinthecircuitofFigure
5.22suchthatthedelaybetweennodesOutandInisminimized.YoumayassumethatCL=64Cg1P210Figure
5.
223.ForthecircuitofFigure
4.11assumethatadriverwithasourceresistanceofisusedtodrivea10cmlong1mmwideAl1wire.Andassumethatthetotallumpedcapacitanceforthiswireequals11pF.WhenapplyingastepinputwithVingoingfrom0tovpleasecomputethepropagationdelayofthecircuit.P151Figure
4.11解答4pleaseanalyzeintrinsiccapacitancesofMOSFETtransistorwriteoutthreesourcesofitanddrawoutMOSFETtransistorcapacitancemodel.P112答基本的MOS结构,沟道电荷以及漏和源反向偏置pn结的耗尽区电容器件模型如下
5.pleasewriteouttheexpressionofequivalentresistanceReqofthecircuitinFigure1whendischargingacapacitor.AssumingthatthesupplyvoltageVDDissubstantiallygreaterthanthevelocity-saturationvoltageVDSATofthetransistor.thechannel-lengthmodulationfactorcannotbeignoredinthisanalysisareknownparameters.P105解答Program
1.pleasewriteoutverilogcodeandtestbenchfora4bitup-counterModulecounterclkresetenablecount;Inputclkresetenable;Output[3:0]count;Reg[3:0]count;Always@posedgeclkIfreset==1’b1Count=0;Elseifenable==1’b1Count=count+1;EndmoduleModulecounter_tb;Regclkresetenable;Wire[3:0]count;CounterU0clkresetenablecount;InitialBeginClk=0;Reset=0;Enable=0;EndAlways#5clk=!clk;initialbegin$monitor$time“clk=%dreset=%denable=%dcount=%d”clkresetenablecount;#100$finishendendmodule
2.pleasewriteoutverilogcodeandtestbenchforabitfulladderModuleaddbitabcisumco;Inputabci;Outputsum.co;Wireabcisumco;Assign{cosum}=a+b+ci ;Endmodulemoduletest_for_addbit;regabci;addbitu1abcisumco;initialbegina=0;b=0;ci=0;#10a=0;b=0;ci=1;#10a=0;b=1;ci=0;#10a=0;b=1;ci=1;#10a=1;b=0;ci=0;#10a=1;b=0;ci=1;#10a=1;b=1;ci=0;#10a=1;b=1;ci=1;#10$finish;endinitial$monitor$time“a=%bb=%bci=%bsum=%bco=%b”abcisumco;endmodule
3.pleasewriteoutverilogcodeandtestbenchfor4-1MUXmodulemuxabcdsely;inputabcd ;input[1 :0]sel ;outputy;regy;always@aorborcordorselcaseselo:y=a;1:y=b;2:y=c;3 :y=d ;Default :$display“errorinsel » ;EndcaseEndmodulemoduletest_for_mux;regabcdsel;//调用DUTmuxu1abcdsely;//产生测试激励信号initialbegina=0;b=1;c=0;d=0;sel=01;#10a=1;b=0;sel=00;#10c=1;a=0;sel=10;#10c=0;d=1;sel=11;#10a=1;b=0;sel=01;#10c=1;a=0;sel=11;#10$finish;end//检测输出信号initial$monitor$time“a=%bb=%bc=%bsel=%by=%b”abcdsely;endmodule4pleasewriteoutverilogcodeandtestbenchfora4bithalfadderModuleadderabsumcarryInput[3:0]ab;Output[3:0]sum;Outputcarry;Reg[3:0]sum;Regcarry;Always@aorbBegin{carrysum}=a+b;EndEndmodulemoduletest_for_adder;reg[3:0]ab;//调用DUTadderu1absumcarry;//产生测试激励信号initialbegina=4’b0000;b=4’b0001;#10a=4’b0001;b=4’b1001;#10a=4’b0010;b=4’b0101;#10a=4’b0100;b=4’b1001;#10a=4’b1000;b=4’b1101;#10a=4’b1001;b=4’b1111;#10a=4’b1100;b=4’b1010;#10a=4’b1101;b=4’b0011;#10$finish;end//检测输出信号initial$monitor$time“a=%bb=%bsum=%bcarry=%b”absumcarry;Endmodule。