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5808880286MICROPRO__SSORSANDISABUS
5.18088MICROPRO__SSORThefirstIBMPCusedthe8088micropro__ssorandmodernPCsstillcarrythatlegacy.The8088isa40-pinmicropro__ssorchipthatcanworkintwomodes:minimummode__ximummode__ximummodeisusedwhenweneedtoconnectthe8088to8087__thcopro__ssor.Ifwedonotneeda__thcopro__ssorthe8088isusedinminimummode.In1978Intelintrodu__dthe16-bitmicropro__ssorcalled
8086.Itwas16-bitbothinternallyandexternally.The8088isinternallyidenticaltothe8086buthasonly8-bitexternaldatabus.Sin__theoriginalIBMPCintrodu__din1981usedthe8088weexplorethe8088insteadofthe
8086.808620GND/S734BHE19CLK18INTR17NMI16AD015AD114AD213AD312AD411AD510AD69AD78AD87AD96AD105AD114AD123AD132AD141GNDRESET21READY222324ALE2526DT/27/M2829HLDA30HOLD31MN/33VCC40AD1539A1638A1737A1836A1935MXWRIORDENINTA32RDTEST808820GND3419CLK18INTR17NMI16AD015AD114AD213AD312AD411AD510AD69AD78A87A96A105A114A123A132A141GNDRESET21READY222324ALE2526DT/27IO/2829HLDA30HOLD31MN/33VCC40A1539A1638A1737A1836A1935MXWRMRDENINTA32RDTESTSS0图5‑1The8086and8088inminimummode
5.
1.1Micropro__ssorbusesEverymicropro__ssor-basedsystemmusth__ethreesetsofseparatebuses:theaddressbusthedatabusthecontrolbusTheaddressbusprovidesthepathfortheaddresstolocatethetargeteddevi__whilethedatabusisusedtotransferdatabetweentheCPUandthetargeteddevi__.Thecontrolbusprovidesthesignalstoindicatethetypeofoperationbeingexecutedsuchasreadorwrite.
5.
1.2Databusin8088Inthe图5‑1pins9-16AD0-AD7areusedbothdataandaddressesin
8088.Atthetimeofthedesignofthemicropro__ssorinthelate1970sduetoICchippackaginglimitationstherewasagreatefforttousetheminimumnumbersofpinsforexternalconnections.ThereforethedesignersmultiplexedtheaddressandthedatabusesmeaningthattheIntelusedthesamepinstocarrytwosetsofinfor__tion:addressanddata.Inthe8088theaddress/databuspinsarenamedAD0-AD7“AD”for“address/data”.ALEaddresslatchenablepinsignalswhethertheinfor__tiononpinsAD0-AD7isaddressordata.Everytimethemicropro__ssorsendsoutanaddressitactivatessetshightheALEtoindicatethattheinfor__tiononpinsAD0-AD7istheaddressA0-A
7.Thisinfor__tionmustbelatchedthenpinsAD0-AD7areusedtocarrydata.WhendataistobesentoutorinALEislowwhichindicatesthatAD0-AD7willbeusedasdatabusesD0-D
7.Thispro__ssofseparatingaddressanddatafrompinsAD0-AD7iscalleddemultiplexing.
5.
1.3Addressbusin8088The8088has20addresspinsA0-A19allowingtoaddressa__ximumofmegabyteofmemory.PinsofAD0-AD7providetheA0-A7addresswiththeassistan__oflatch.Todemultiplextheaddresssignalsfromtheaddress/datapinsalatchmustbeusedtograbtheaddress.Themostwidelyusedlatchisthe74LS373ICseefiguresasthefollowing.�1��8088A7A6A5A4A3A2A1A074LS373DQOCD7D6D5D4D3D2D1D0AD7AD6AD5AD4AD3AD2AD1AD0AD0AD7A8ALEA19A15GA19A8A15MN/MXVCC12-bitAddressBus8-bitAddressBusDataBus图5‑2RoleofALEinaddress/datademultiplexing�1�FunctionTableOutputControlGDEnableDQVccGNDOCCLK1Q1D8D2D3D4D5D6D7D2Q3Q4Q5Q6Q7Q8QOutputControlGEnableHHLXLLLHHLXXOutputHLQZ图5‑374LS373DlatchAD0toAD7ofthe8088gointothe74LS373latch.ALEprovidesthesignalforthelatchingaction.Forthe8088theoutputof74LS373providesthe8-bitaddressA0-A7whileA8-A15comedirectlyfromthemicropro__ssorpins2-8andpin
39.Thelast4-bitaddresscomefromA16-A19pinnumbers35-
38.Inanysystemalladdressesmustbelatchedtoprovideastablehigh-drive-capabilityaddressbusforthesystem.�1�WRIO/RDMMEMRMEMWIORIOWENLatchD7D
0...A0A
7...LatchLatchA19A
5.
1.48088controlbusThereare__nycontrolsignalsassociatedwiththe8088CPUhoweverfornowwediscussthosethatwithreadandwriteoperations.The8088canac__ssbothmemoryandI/Odevi__sforreadandwriteoperations.Fourcontrolsignalsare:MEMRmemoryreadMEMWmemorywriteIORI/OreadIOWI/OwriteThe8088providesthreecontrolsignals:RDWRandIO/-M.TheRDandWRpinsarebothactivelow.IO/-MislowformemoryandhighforI/Odevi__.Fromthesethreepinsfourcontrolsignalsaregenerated:IORIOWMEMRMEMWasshownin图5‑4andlistedin表5‑
1.表5‑1ControlsignalgenerationRDWRIO/-MSignal010-MEMR100-MEMW011-IOR101-IOW00xNeverhappens
5.
1.5Bustimingof8088The8088uses4clocksformemoryandI/Obusactivities.ForexampleinthereadtimingALElatchestheaddressinthefirstclock.Insecondandthirdclockcyclesthereadsignalisprovided.FinallybytheendofthefourthclockcyclethedatamustbeatthepinsoftheCPUtobefetched.CLKT1T2T3T4AD0~AD7A8~A19ALEMEMRAddressData图5‑5ALETimingNoti__thattheentirereadorwritecycletimeisonly4clockcycles.Ifthetaskofreadingorwritingtakesmorethan4clocksduetotheslownessofmemoryorI/Odevi__swaitstatusWScanberequestedfromtheCPU.
5.
1.6Pinsof8088inminimummodePins24-32ofthe8088h__edifferentfunctiondependingonwhetherthe8088isusedinminimummodeor__ximummode.
5.
1.
6.1Pin24-INTAinterruptacknowledgeActive-lowoutputsignal.InformsinterruptcontrollerthatanINTRhasoccurredandthatthevectornumberis__ailableonthelow8binesofthedatabus.
5.
1.
6.2Pin25ALEaddresslatchenableActive-highoutputsignal.Indicatesthatavalidaddressis__ailableontheexternaladdressbus.
5.
1.
6.3Pin26-DENdataenableActive-lowoutputsignal.Enablesthedatatrans__iversuchas74LS
245.ThisallowsisolationoftheCPUfromthesystembus.
5.
1.
6.4Pin27DT/-Rdatatran__it/re__iveThissignalisusedtocontrolthedirectionofdataflowthroughthedatatrans__iver74LS
245.
5.
1.
6.5Pin28IO/-Minput-outputormemoryIndicateswhetheraddressbusisac__ssingmemoryorI/Odevi__.In8088itislowwhenac__ssingmemoryandhighwhenac__ssingI/Odevi__.
5.
1.
6.6Pin29-WRwriteActive-lowoutputsignal.IndicatesthatthedataonthedatabusisbeingwrittentomemoryorI/Odevi__.
5.
1.
6.7Pin32-RDreadActive-lowoutputsignal.IndicatesthatthedataonthedatabusisbeingbroughtinfrommemoryorI/OtotheCPU
5.
1.
6.8Pin31HOLDholdActive-highinputsignal.ThissignalinputfromtheD__controllerthatindicatesthatthedevi__isrequestingac__sstomemoryandI/Ospa__andthattheCPUshouldreleasecontrolofthelocalbus.
5.
1.
6.9Pin30HLDAholdacknowledgeActive-highoutputsignal.AfterinputonHOLDtheCPUrespondswithHLDAtosignalthattheD__controllercanbeusedbus.
5.
1.7Other8088pins
5.
1.
7.1Pin33MN/-MXminimum/__ximumMinimummodeisselectedbyconnectingMN/-MXdirectlyto+5V;__ximummodeisselectedbygroundingthispin.
5.
1.
7.2Pin17__Inon-__skableinterruptThisisanedged-triggeredfromlowtohighinputsignaltopro__ssorthatwill__kethemicropro__ssorjumptotheinterruptvectortableafteritfinishesthecurrentinstruction.
5.
1.
7.3Pin18INTRinterruptrequestINTRisanactive-highlevel-triggeredinputthatiscontinuouslymonitoredbythemicropro__ssorforanexternalinterrupt.Thispinand–INTAareconnectedtothe8259interruptcontrollerchip.
5.
1.
7.4Pin19CLKclockMicropro__ssorsrequireaveryaccurateclockforsynchronizationofeventsanddrivingtheCPU.ForthisreasonIntelhasdesignedthe8284clockgeneratortobeusedwiththe
8088.CLKisaninputandisconnectedtothe8284clockgenerator.ItactsastheheartbeatoftheCPU
5.
1.
7.5Pin22READYreadyREADYisinputsignalusedtoinsertawaitstateforslowermemoriesandI/O.Itinsertswaitstateswhenitislow.TheREADYsignalisneededtointe_____theCPUtolow-speedmemoriesandI/Odevi__s.
5.
1.
7.6Pin23-TESTtestInminimummodethisisnotused.In__ximumhoweverthisisaninputfrom8087__thcopro__ssortocoordinatecommunicationsbetweenthetwopro__ssors.
5.
1.
7.7Pin21RESETresetToterminatethepresentactivitiesofthemicropro__ssorahighisappliedtotheRESETinputpin.Apresen__ofhighwillfor__themicropro__ssortostopallactivityandset__jorregisterstothevaluesshownin表5‑
2.表5‑2IPandsegmentregisterscontentsafterresetRegisterContentsCSFFFFIP0000DS0000SS0000ES0000Accordingto表5‑2whenpowerisappliedtothe8088itwakesupatphysicaladdressFFFF0Hsin__aCS:IPaddressofFFFF:0000leadstoaphysicaladdressofFFFF0H.Thereforewemusth__eanon-volatilememorysuchasROMattheFFFF0Haddress.
5.28284AND8288SUPPORTINGCHIPSInoriginalIBMPCintrodu__din1981usedthe8088in__ximummodewithasocketforthe8087__tcopro__ssor.In__ximummodethe8088requirestheuseof8288togeneratesomecontrolsignals.Modernmicropro__ssorssuchasPentiumh__eallthesechipsincorporatedintoasinglechip.808620GND/S734BHE19CLK18INTR17NMI16AD015AD114AD213AD312AD411AD510AD69AD78AD87AD96AD105AD114AD123AD132AD141GNDRESET21READY2223QS124QS02526272928MN/33VCC40AD1539A16/S338A17/S437A18/S536A19/S635MXLOCKS2S1S032RDTEST808820GNDHIGH3419CLK18INTR17NMI16AD015AD114AD213AD312AD411AD510AD69AD78A87A96A105A114A123A132A141GNDRESET21READY2223QS124QS02526272829/30/31MN/33VCC40A1539A16/S338A17/S437A18/S536A19/S635MXLOCKS2S1S032RDTEST/30/31GT1RQGT0RQGT0RQGT1RQ图5‑6The8086and8088in__ximummode
5.
2.18288buscontroller8288MRDC1IOBVCC202CLK34DT/5ALE6789MWTC10GND18MCE/PDEN17DEN16CEN151419131211S0S1RAENAMWCS2INTAIORCAIOWCIOWC图5‑78288buscontrollerAsshownin图5‑7the8288isthe20-pinchipspeciallydesignedtoprovideallthecontrolsignalswhenthe8088isinthe__ximummode.
5.
2.
1.1Inputsignals
5.
2.
1.
1.1-S0-S1-S2StatusinputInputtothesepinscomefromthe
8088.DependingupontheinputfromtheCPUthe8288willprovideoneofcom__ndsorcontrolsignalsshownin表5‑
3.表5‑3Statuspinsofthe8288S2S1S0ProcessorState8288Com__nd000Interruptacknowledge-INTA001Readinput/outputport-IORC010Writeinput/outputport-IOWC-AIOWC011HaltNone100Codeac__ss-MRDC101Readmemory-MRDC110Writememory-MWTC-AMWTC111PassiveNone
5.
2.
1.
1.2CLKclockThisisinputfromthe8284clockgeneratorprovidingtheclockpulsetothe8288tosynchronizeallcom__ndandcontrolsignalswiththeCPU.
5.
2.
1.
1.3-AENaddressenableAnactive-lowsignalactivatesthe8288com__ndoutputatleast115nsafteritsactivation.IntheIBMPCitisconnectedtotheAENgenerationcircuitry.
5.
2.
1.
1.4__Ncom__ndenableAnactive-highsignalisusedtoactive/enablethecom__ndsignalsandDEN.IntheIBMPCitisconnectedtotheAENgenerationcircuitry.
5.
2.
1.
1.5IOBinput/outputbusmodeAnactive-highsignal__kesthe8288operateininput/outputbusmoderatherthaninsystembusmode.Sin__theIBMPCisdesignedwithsystembusesitisconnectedtolow.
5.
2.
1.2Outputsignals
5.
2.
1.
2.1-MRDCmemoryreadcom__ndThisisactive-lowandprovidesthe–MEMRmemoryreadsignal.Itactivatestheselecteddevi__ormemorytoreleaseitsdatatothedatabus.
5.
2.
1.
2.2-MWTCmemorywritecom__nd-AMWCadvan__dmemorywritecom__ndThesetwoactive-lowsignalsareusedto____memorytorecordthedatapresentonthedatabus.Thesetwoarethesameasthe–MEMWmemorywritesignaltheonlydifferen__beingthat–AMWCisactivatedslightlyearlierinordertogiveextratimetoslowdevi__s.
5.
2.
1.
2.3-IORCI/Oreadcom__ndThisisanactive-lowsignalthat____stheI/Odevi__toreleaseitsdatatothedatabus.InthePCitiscalled–IORI/Oreadcontrolsignal.
5.
2.
1.
2.4-IOWCI/Owritecom__nd-AMWCadvan__dI/Owritecom__ndBothareactive-lowsignalsusedto____theI/Odevi__topickupthedataonthedatabus.–AIOWCis__ailablealittlebitearliertogivesufficienttimetoslowdevi__s.InthePC-IOWCiscalled–IOWI/Owritecontrolsignal.
5.
2.
1.
2.5-INTAinterruptacknowledgeAnactive-lowsignalwillinformtheinterruptingdevi__thatitsinterrupthasbeenacknowledgedandwillprovidethevectoraddresstothedatabus.IntheIBMPCthisisconnectedtoINTAofthe8259interruptcontrollerchip.
5.
2.
1.
2.6DT/-Rdatatran__it/re__iveDT/-Risusedtocontrolthedirectionofthedatainandoutofthe
8088.IntheIBMPCitisconnectedtoDIRofthe74LS
245.Whenthe8088iswritingdatathissignalishighandwillallowdatagofromtheAsidetotheBsideofthe74LS245sothatdataisreleasetothesystembus.ConverselywhenthePCisreadingdatathissignalislowwhichallowsdatatocomeinfromtheBsidetotheAsideofthe74LS245datatrans__iverchipsothatitcanbere__ivedbytheCPU.
5.
2.
1.
2.7DENdataenableAnactive-highsignalwill__kethedatabuseitheralocaldatabusorthesystemdatabus.IntheIBMPCitisusedalongwithasignalfromthe8259interruptcontrollertoactivateGofthe74LS245trans__iver.
5.
2.
1.
2.8M__/PDEN__stercascadeenable/peripheraldataenableThisisusedalongwiththe8259interruptcontrollerin__sterconfiguration.IntheIBMPCthe8259isusedasasl__ethereforethispinisignored.
5.
2.
1.
2.9ALEaddresslatchenableALEisanactive-highsignalusedtoactivateaddresslatches.The8088multiplexesaddressanddatathroughAD0-AD7inordertos__epins.IntheIBMPCALEisconnectedtotheGinputofthe74LS373__kingdemultiplexingoftheaddressespossible.
5.
2.28284clockgeneratorThe8284isusedinbothminimumand__ximummodesin__itprovidestheclockandtimingforthe8088-basedsystem.8284A9GND1CSYNC2PCLK34RDY15READY6RDY278CLKRESET10VCC18X117X21615EFI14F/13OSC1211AEN1AEN2CRESASYNC图5‑88284chipThisan18-pinchipespeciallydesignedforusewith8088/86micropro__ssor.
5.
2.
2.1Inputpins
5.
2.
2.
1.1-RESresetinThisisaninputactive-lowsignaltogenerateRESET.IntheIBMPCitisconnectedtothepower-good电源完好signalfromthepowersupply.WhenthepowerswitchintheIBMPCisturnedonassumingthatthepowersupplyisgoodalowsignalisprovidedtothispinandthe8284inturnwillactivatetheRESETpinforcingthe8088toresetthenthemicropro__ssortakesover.Thiscalledcoldboot.
5.
2.
2.
1.2X1andX2crystalinX1andX2arethepinstowhichacrystalisattached.Thecrystalfrequencymustbe3timesthedesiredfrequencyforthemicropro__ssor.The__ximumcrystalforthe8284Ais24MHz.TheIBMPCisconnectedtoacrystalof
14.31818MHz.
5.
2.
2.
1.3F/-Cfrequency/clockThispinprovidesanoptionforthewaytheclockisgenerated.Ifconnectedtolowtheclockisgeneratedbythe8284withthehelpofacrystaloscillator.Ifitisconnectedtohighitexpectstore__iveclocksattheEFIpin.Sin__theIBMPCusesacrystalthispinisconnectedtolow.
5.
2.
2.
1.4EFIexternalfrequencyinExternalfrequencyisconnectedtothispinifF/-Chasbeenconnectedtohigh.IntheIBMPCthisisnotconnected.
5.
2.
2.
1.5CSYNCclocksynchronizationThisisanactive-highsignalisusedtoallowseveral8294chipstobeconnectedtogetherandsynchronized.TheIBMPCusesonlyone8284thereforethispinisconnectedtolow.
5.
2.
2.
1.6RDY1and-AEN1RDY1isactive-highand-AENisactive-low.Thesearetogethertoprovideareadysignaltothemicropro__ssorwhichwillinsertaWAITstatetotheCPUread/writecycle.InthePCRDY1isconnectedtoD__WAIT-AEN1isconnectedtoRDY/WAIT.ThisallowsawaitstatetobeinsertedbyeithertheCPUorD__.
5.
2.
2.
1.7RDY2and-AEN2ThesefunctionexactlylikeRDY1and-AEN1butaredesignedtoallowforamultipro__ssingsystem.IntheIBMPCRDY2isconnectedtolowand-AEN2isconnectedtohigh.
5.
2.
2.
1.8-ASYNCThiscalledreadysynchronizationselect.Anactivelowisusedfordevi__sthatarenotableaadheretoverystrictRDYsetuptimerequirement.IntheIBMPCthisisconnectedtolow__kingthetimingdesignofthesystemeasierwithslowerlogicgates.
5.
2.
2.2Outputsignals
5.
2.
2.
2.1RESETThisisanactive-highsignalthatprovideaRESETsignaltothe
8088.
5.
2.
2.
2.2OSCoscillatorThisprovidesaclockfrequencyequaltothecrystaloscillatorandisTTLtransistor-transistorlogicalcompatible.Sin__theIBMcrystaloscillatoris
14.31818MHzOSCwillprovidethisfrequencytotheexpansionslotoftheIBMPC.
5.
2.
2.
2.3CLKclockThisisanoutputfrequencyequaltoone-thirdofthecrystaloscillatororEFIinputfrequencywithadutycycle占空因数of33%.Thisisconnectedtotheclockinputofthe8088andallotherdevi__sthatmustbesynchronizedwiththeCPU.IntheIBMPCitisconnectedtopin19CLKofthe8088micropro__ssorandothercircuitryundertheCLK88label.Thisfrequency4772776MHz14318318dividedby3isthepro__ssorfrequencyonwhichalloftimingcalculationsofthememoryandI/Ocyclearebased.
5.
2.
2.
2.4PCLKperipheralclockPCLKisone-halfofclockorone-sixthofthecrystalwithadutycycleof50%andisTTLcompatible.IntheIBMPCthisis
2.___383MHzisprovidedtothe8253timertobeusedtogeneratespeakertonesandforotherfunctions.
5.
2.
2.
2.5READYThissignalisconnectedtoREADYoftheCPU.IntheIBMPCitisconnectedtosignalthe8088thattheCPUneedstoinsertawaitstateduetotheslownessofthedevi__sthattheCPUistryingtocontact.
5.38-BITSECTIONOFISABUSPrevioussectionsh__eexplainedthe8088CPUandsupportingchips.ThissectionwillexplainhowtheyareconnectedintheoriginalIBMPCtoprodu__therequiredbusestocommunicatewithmemoryinput/outputperipheralsandthe8-bitsectionoftheISAbus.Thestudyofthe8-bitsectionisthe__intopicofthissection.
5.
3.1AbriefofbushistoryTheoriginalIBMPCintrodu__din1981usedan8088micropro__ssorwhose8-bitdatabusg__ebirthtothe8-bitsectionoftheISAbus.In1984whenIBMintrodu__dtheIBMPC/ATusingthe80286micropro__ssorthedatabuswasexpandedto16bits.The8-bitdatabuscanbeseenasasubsectionofthe16-bitISAbus.Veryoftenthe8-bitdatabuswasreferredtoastheIBMPC/XTextendedtechnologybusinordertodifferentiateitfromtheIBMPCATadvan__dtechnology.EventuallytheIBMPCATbusbecameknownastheISAIndustryStandardArchitecturebussin__theterm“PCAT”wascopyrightedbyIBM.
5.
3.2Localbusvs.systembusInthediscussionofPCdesignweoftenseethetermslocalbusandsystembus.Thesystembusnotonlyprovidesne__ssarysignaltoallthechipsRAMROMandperipheralchipsonthemotherboardbutalsogoestotheexpansionslotforanyplug-inexpansioncard.IncontrastthelocalbusisconnecteddirectlytotheCPU.AnycommunicationwiththeCPUmustgothroughthelocalbus.Thereisthebridgebetweenthelocalbusandthesystembusto__kesuretheyareisolatedfromeachother.Sometimesthesystembusisreferredtoasaglobalbus.Weusetri-statebufferstoisolatethelocalbusandsystembus.Forexample74LS245iswidelyusedchipforthedatabusbuffersin__itisbidirectional.�1�GFunctionTableVccGNDB1A1A8A2A3A4A5A6A7B2B3B4B5B6B7B8DirctionControlDIREnableEnableGDirctionControlDIROperationLLHLHXBdatatoAbusAdatatoBbusIsolation图5‑974LS245bidirectionalbufferThefollowingfigureshowsanexampleoflocalandsystembuses.X74LS373OEGaddr/data20-bit8-bit74LS245GDIR8288ALEDT/DENS2S1S0AENINTACENMEMRMEMWIORIOWA0A19D0D7AEN20-bit8-bitdata8088AD0~AD7A8~A19AddressBusSYSTEMBUSDataBusControlBusResetReadyCLK8284ACLKAENMN/MX8259INTAD0D7SPEN/AENINTRRESETresetdriveCLK8088S0S1S2RLOCALBUS图5‑108088connectionandbusesinthePC/XTFigure图5‑10givesanoverviewofthe8088anditssupportingchipsasdesignedintheoriginalPC.Noti__theroleofthe74LS245and74LS373inisolatingthelocalandsystembuses.Everythingontheleftofthe828874LS373sand74LS245representthelocalbusandeverythingontherightsideofthosechipsarethesystembus.The74LS245and74LS373splaytheroleofbridgetoisolatethelocalandsystembuses.
5.
3.3AddressbusThree74LS373chipsin图5‑10areusedfortwofunctions:1Tolatchtheaddressesfromthe8088andprovidestableaddressestotheentirecomputer.Theaddressbusisaunidirectionalbus.The74LS373chipsareactivatedbycontrolsignalsAENandALE.WhenAENislowthe8088providestheaddressbusestothesystem.The8288’sALEconnectedtoGenablesthe74LS373tolatchtheaddressfromtheCPUprovidinga20-linestableaddressestomemoryperipheralsandexpansionslots.DemultiplexingaddressA0-A7isperformedbythe74LS373connectedtopinsAD0-AD7oftheCPU.TheCPU’sA8-A15isconnectedtothesecond74LS373andA16-A19tothethirdone.Halfofthethird74LS373isunused.2Toisolatethesystemaddressbusesfromlocaladdressbuses.ThesystembusesmustbeallowedtobeusedbytheD__oranyotherboardthroughtheexpansionslotwithoutdisturbingtheCPU.Thisisachievedbythe74LS373sthroughAEN.
5.
3.4DatabusThebidirectionaldatabusgoesthroughthe74LS245trans__iver.DT/-RandDENarethetwosignalsthatactivatethe74LS
245.DT/-RgoestoDIRofthe74LS245and__kesthetrans__ivertran__itinfor__tionfromAsidetoBsidewhenDT/-Rishigh.ConverselywhenDT/-R__kesDIRlowthetrans__ivertransfersinfor__tionfromBsidetoAsidetherebyre__ivinginfor__tionfromthesystemdatabusandbringingittothemicropro__ssor.DENenablesthe74LS
245.Thisisolatesthedatabusesto__kethemeitheralocalbusorasystembus.Whenthe74LS245isnotactivethesystemdatabusisisolatedfromthelocaldatabus.
5.
3.5ControlbusThefourmostimportantcontrolsignalsoftheIBMPCare–IOR-IOW-MEMRand–MEMW.Theyareprovidedbythe8288chipasshownin图5‑
10.Thetimingforthebusactivityisshownin图5‑
11.T2T4T3T1RCLKA8~A19AD0~AD7ALEMEMRAddressDataDT/DEN图5‑11ALEDENandDTRtimingforthe8088system
5.
3.6Onebustwo__sterWhilethe8088the__inpro__ssorisdesignedforfetchingandexecutinginstructionsitisunac__ptablyslowfortransferringlargenumberofbytesofdatasuchasinharddiskdatatransfers.Insteadthe8237chipisusedfordatatransfersoflargenumberofbytes.The8237’sjobistotransferdataanditmusth__eac__sstoallthreebusestodothat.Sin__nobuscanservetwo__stersatthesametimetheremustbeawaytoalloweitherthe8088pro__ssororthe8237D__togaincontroloverthebuses.Thisiscalledbusarbitration总线仲裁andisactivatedbytheAENaddressenablegenerationcircuitry.
5.
3.7AENsignalgenerationWhenthesystemisturnedonthe8088CPUisincontrolofallthebuses.TheCPU__intainscontrolaslongasitisfetchingandexecutinginstructions.AscanbeseenfromthefollowingfigureAENistheoutputsignaloftheDflip-flop.Sin__QiseitherhighorlowdependingonthestatusofthissignaleithertheCPUortheD__canac__ssthebuses.�1�≥1X74LS17574LS7474LS175S1clrQ3clockDQD0Q0clockclockQpreclrQ0AENS0S2LOCKVccVccfrom8088from8237HRQDMAfromclk88of8284A≥1HLDAto8237resetD3clrAEN08088Buses18237DMABusesAEN图5‑12ALEgenerationcircuitryinthePC/XT
5.
3.8ControlofthebusbyD__HowdoesAENbecomehighhandingcontrolofthesystembusestoD__WhenD__re__ivesarequestforservi__itwillnotifytheCPUthatitneedstousethesystembusesbyputtingaLOWonHRQD__thisisthesameastheHOLDsignalinminimummodeofthe
8088.ThisinturnwillprovideahighontheD3inputofthe74LS175四d触发器assumingthatthecurrentmemorycycleisfinishedandtheLOCKisnotactivated.InthefollowingclockcycleHLDAholdacknowledgeisprovidedtotheD__andAENbecomeshighgoingcontroloverthebusestotheD__.
5.
3.98-bitsectionoftheISAbusTheoriginalIBMPChadan8-bitdatabuslaterwiththeintroductionofthe80286the16-bitversionofthebusbecame__ailable.The80286busbecameknownastheISAbus.The8-bitisasubsetofthe16-bitISAbusandusedin__nyperipheralboards.�GNDB1A1RESETDRV+5VDC1RQ9-5VDCDRQ2-12DCOWS+12DC-SMEMW-SMEMR-IOW-IOR-DACK3DRQ3-DACK1DRQ1-REFRESHCLKIRQ7IRQ6IRQ5IRQ4IRQ3-DACK2T/CBALE+5VDCOSCGNDGNDB10B20B31A10A20A31-I/OCHCKSD7SD6SD5SD4SD3SD2SD1SD0-I/OCHRDYAENSA19SA18SA17SA16SA15SA14SA13SA12SA11SA10SA9SA8SA7SA6SA5SA4SA3SA2SA1SA0REARPANELSIGNALNAMESIGNALNAME图5‑13ISAIBMPCATbusslotsignalsdetail8-bitselectionAddressesA0-A19anddatasignalsD0–D7areontheAsideoftheexpansionslotontheAsidealsonoti__theAENpin.OntheBsidearefoundcontrolsignalsIORIOWMEMRMEMW.The–signontheseandothercontrolsignalsimpliesanactivelowsignal.
5.480286MICROPRO__SSORThe80286isa68-pinmicropro__ssor.The80286canworkinoneoftwomodes:realmodeorprotectedmode.Inrealmodethe__ximummemoryitcanac__ssis1M00000HtoFFFFFH.Inrealmode80286isafasterversionofthe8086withafewnewinstructions.Toac__sstheentire16Mbytesofmemory000000HtoFFFFFFHitmustworksinprotectedmode.Whenpowerisappliedtothe80286itstartsupinrealmodeandcanbeswitchedtoprotectedmodeatanytimethroughasoftwareinstruction.5150494847464544434241403938373635343332313029282726252423222120191852535455565758596061626364656667681234567891011121314151617RESETCOD/INTAA0A1A2CLKVccA3A4A5A7A7A8A9A10A11A12A13M/IOLOCKHLDAHOLDREADYVccPEREQVssNMIN.C.INTRN.C.N.C.BUSYERRORCAPD15D7D14D6D13D5D12D4D11D3D10D2D9D1D8D0VssPEACKA17A14A15A16A18A19A20A21VssA22A23S0S1N.C.N.C.BHE图5‑1480286Micropro__ssor
5.
4.1PinsA0-A23addressbusTheseoutputsignalsprovidea24-bitaddresstobeusedbythedecodingcircuitrytolocatememoryorI/O.Whenprovidinganaddressformemoryall24pinsmustbeusedthereforeitcanbeac__ssa__ximumof16Mbytesofmemory224=16M.Toac__ssanI/OaddressonlyA0-A15areused.IftheI/Oaddressisa16-bitaddressA0-A15areusedtoprovidetheaddressandpinsA16-A23arelow.IftheI/Oaddressisan8-bitaddressonlyA0-A7areusedandA8-A23arealllow.
5.
4.2PinsD0-D15databusThesepinsprovidethe16-bitpathfordatatobetransferredinandoutoftheCPU.Itmustbenotedthatunlikethe8088thedatabusisnotmultiplexed.Theuseofseparatepinsforaddressanddataresultsinhigherpincountsbuts__estimesin__iteliminatestheneedfordemultiplexer.This2-bytedatapathtotheCPUallowsthetransferofdataonbothbytesoroneitherbytedependingontheoperation.The80286coordinatestheactivityontheD0-D15databuswiththehelpofA0andBHE.
5.
4.3Pin-BHEbushighenableThisisanactive-lowoutputsignalusedtoindicatethatdataisbeingtransferredonD8-D
15.表5‑4BHEA0andbyteselectioninthe80286BHEA0DataBusStatus00Transferring16-bitdataonD0-D1501TransferringabyteontheupperhalfofdatabusD8-D1510TransferringabyteonthelowerhalfofdatabusD0-D711Reservedthedatabusisidle
5.
4.4PinCLKclockCLKisaninputprovidingtheworkingfrequencyforthe
80286.Thepro__ssoralwaysworksonhalfofthisfrequency.ForexampleifCLK=16MHzthesystemisan8MHzsystem.
5.
4.5PinM/-IOmemoryI/OselectM/-IOisanoutputsignalusedbytheCPUtodistinguishbetweenI/Oandmemoryac__ss.Whenitishighmemoryisbeingac__ssedandwhenitislowI/Oisbeingac__ssed.
5.
4.6PinCOD/-INTAcode/interruptacknowledgeThisisanoutputsignalusedbytheCPUtoindicatewhetheritisperformingmemoryread/writeofdataoraninstructionfetch.ItisalsousedtodistinguishbetweentheactionofinterruptacknowledgeandI/Ocycle.ThissignalalongwiththestatussignalsandM/-IOisusedtodefinethebuscycle.
5.
4.7Pin-S1and-S0statussignalsThesestatussignalsforthebuscyclearebothoutputsignalsusedbytheCPUalongwithM/-IOandCOD/-INTAtodefinethetypeofbuscycle.
5.
4.8PinsHOLDandHLDAHOLDandHLDAallowtheCPUtocontrolthebus.HOLDisaninputsignaltothe80286andactivehigh.Itisusedbythedevi__suchasD__torequestpermissiontousethebus.InresponsetheCPUactivatestheoutputsignalHLDAbyputtingahighonittoinformtherequestingdevi__thatishasreleasedthebusesforthedevi__’suse.TheD__hascontroloverthebusesaslongasHOLDishighandinresponsetheCPUkeepsHLDAhigh.WhenevertheD__bringsHOLDlowtheCPUrespondsby__kingHLDAlowandregainscontroloverthebuses.
5.
4.9PinRESETThisisaninputsignalandactivehigh.Whenthereisalow-to-hightransitiononRESETanditstayshighforatleast16clocksthe80286initializesallregisterstotheirpredefinedvaluesandtheoutputpinsofthe80286willh__ethestatusshowninthefollowingtable.表5‑5PinstatusbusidleduringresetPinNameSignalLevelduringResetD0-D15HighImpedan__阻抗A0-A23HighW/-RLowM/-IOHighAslongastheRESETpinishighnoinstructionorbusactivityisallowed.Thecontentsoftheinstructionpointerandsegmentregistersofthe80286afterRESETareshowninthefollowingtable.表5‑6IPandsegmentregistersafterRESETRegisterContentsCSF000IPFFF0DS0000ES0000SS0000Itmustbenoti__dthatwhenRESETofthe80286isactivateditfor__sthe80286toenterintorealmode.Inrealmodethe80286indeedallthex86sfromthe80286tothePentium4pro__ssorcanaddressonly1megabytessin__itusesonlyaddresslineA0-A
19.Sin__RESETalsocausesA20-A23tobehighthefirstinstructionforthe80286mustbeatphysicaladdressFFFFF0H.ThisisduetothefactthatatresetCS=F000andIP=FFF0__kingthelogicaladdressofthefirstinstructionF000:FFF
0.ThisprovidesthephysicaladdressofFFFFF0HonA0-A19andsin__A20-A23ishighatresetthephysicaladdressofthefirstinstructionmustbeFFFFF0Hthisis16bytesfromthetopofthe16Maddressrangeofthe
80286.The80286expectstoh__eafarjumpatlocationFFFFF0HandwhentheJMPisexecutedthe286puts0sonpinsA20-A23__kingiteffectivelya1Mrangerealmodesystem.
5.
4.10PinINTRinterruptrequestINTRisanactive-highinputsignalintothe80286requestingsuspensionofthecurrentprogramexecution.Itisusedforexternalhardwareinterruptexpansionalongwiththe8259interruptcontrollerchip.
5.
4.11Pin__Inon__skableinterruptrequest__Iisanactive-highinputsignal.Whenthispinisactivatedthe80286willauto__ticallyperforminstructionINT
2.
5.
4.12Pin-READY-READYisanactive-lowinputsignalusedtoinsertawaitstatusandconsequentlyprolongthereadandwritecycleforslowmemoryandI/Odevi__s.
5.
4.13-LOCKPEREQ-BUSY-ERRORand-PEACKThesefivesignalscoordinatebusactivitieswiththe__thcopro__ssor.
5.
4.1480286TimingThefollowingfigureshowsthe80286timing.Noti__the2-clocktimeforread.TsTsTcTcPCLKA0~A23READYpreviouscyclereadcyclenextcycleD0~D15ALEDT/DENRMEMR图5‑15ALEDENandDTRtimingforthe80286CPU
5.516-BITISABUSTheoriginaloftechnicalspecificationsof__nyoftoday’sx86PCsisthe80286-basedIBMPC/AT.MuchofthePC/ATinturnisbasedontheoriginal8088-basedIBMPCintrodu__din
1981.A__jorlegacyoftheoriginalPCsistheISAIndustryStandardArchitecturebusslot.Thefollowingfigureshowsthe80286micropro__ssoralongwithsupportingchipsusedintheoriginalPC/ATcomputers.8228480286A23A22A21A20A19M/IO...A2A1A0D15D8D7D0BHEA
18......CLKREADYS0S1A20ArbitrationCircuitry82288BHEIOWIORMEMWMEMRControlSignal24-bitAddressBus16-bitDataBusA20control图5‑1680286blockdiagramandsupportingchipsinthePCATTheaddressdataandcontrolbusesinthisfigureareusedthroughoutthemotherboardandarealsoprovidedtotheISAexpansionslot.Intoday’sPCthe80286isrepla__dwithIntel’sPentiumorAMD’sAthlonmicropro__ssorandallthecontrolsignalsareprovidedbyachipset.AchipsetisanICchipcontainingallthecircuitryneededtosupporttheCPUinagivenmotherboard.�GNDB1A1RESETDRV+5VDC1RQ9-5VDCDRQ2-12DCOWS+12DC-SMEMW-SMEMR-IOW-IOR-DACK3DRQ3-DACK1DRQ1-REFRESHCLKIRQ7IRQ6IRQ5IRQ4IRQ3-DACK2T/CBALE+5VDCOSCGNDGNDB10B20B31A10A20A31-MEMCS16-I/OCS16IRQ10IRQ11-I/OCHCKSD7SD6SD5SD4SD3SD2SD1SD0-I/OCHRDYAENSA19SA18SA17SA16SA15SA14SA13SA12SA11SA10SA9SA8SA7SA6SA5SA4SA3SA2SA1SA0REARPANELSIGNALNAMESIGNALNAMEIRQ12IRQ13IRQ14-DACK0DRQ0-DACK5DRQ5-DACK6DRQ6-DACK7DRQ7+5VDC-MASTRGNDSBHELA23LA22LA21LA20LA19LA18LA17-MEMR-MEMWSD08SD09SD10SD11SD12SD13SD14SD15D1C1D10D18C10C18COMPONENTSIDE图5‑17ISAIBMPCATbusslotsignals
5.
5.1AddressbusAddressesA0-A19arelatchedusingALE.Theseaddressesareusedthroughoutthemotherboardandarealsoprovidedto62-pinpartoftheISAslotasSA0-SA19systemaddress.See图5‑
17.TheA20-A23partoftheaddressisprovidedinthe36-pinsection.In36-pinsectionoftheISAslotA17-A23arealsoprovidedasLA17-LA23latchableaddress.WeneedtousetheALEsignaltolatchtheseaddressesinthedesignofplug-incards.TheALEsignalisprovidedasBALEbufferedALEandcanbeusedtolatchLA17-LA
23.
5.
5.2DatabusThedatabusiscomposedofpinsD0-D
15.Thedatabusisbufferedbyapairof74LS245databustrans__iversthatareusedthroughoutthemotherboardtoac__ssmemoryandports.TheyarealsoprovidedattheexpansionslotasSD0-SD15systemdata.Howeveritmustbenoti__dthatSD0-SD7areprovidedatthe62-pinpartinorderto__keitcompatiblewiththeoriginal8088-basedPC/XTwhileSD8-SD15showuponthe36-pinpart.Toselecttheupperbyteorlowbyteof16-bitdataweuseBHEbushighenable.BHEislatchedandusedonthesystemboardandalsoprovidedattheexpansionslotunder__HEsystembushighenable.
5.
5.3MemoryandI/OsignalsIORandIOWaretwocontrolsignalsusedtoac__sspartsthroughoutthesystem.Theyareshowuponthe62-pinsectionoftheISAexpansionslot.SignalsMEMRMEMW__EMRand__EMWareusedtoac__ssmemory.MEMRandMEMWcanbeusedtoac__ssmemoryinanylocationbuttoac__ssmemorywithinthe1megabyterangewemustuse__EMRand__EMWonthe62-pinpartoftheISA.
5.
5.4OddandEvenbytesandBHEX�A19~A1OddBank000010000300005D15~D8D8A0BHEFFFFFEvenBank000000000200004D7D0FFFFED7~D0lowbytehighbyteevenbyteoddbyteD15D8D7D0D15D8D7D0D15D8D7D0D15evenbyteoddbyteevenbyteoddbyteA0BHE01EvenbyteD7~D001OddbyteD15~D800EvenwordD15~D0图5‑18Oddandevenbanksofmemoryin16-bitCPUs。