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6MEMORYANDMEMORYINTE___CING
6.1SEMICONDUCTORMEMORYFUNDAMENTALSInthedesignofallcomputerssemiconductormemoriesareusedaspri__rystorageforcodeanddata.SemiconductormemoriesareconnecteddirectlytotheCPUandtheyarethememorythattheCPUfirstasksforinfor__tioncodeanddata.Forthisreasonsemiconductormemoriesarereferredtoaspri__rymemory.
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1.1MemorycapacityThenumberofbitsthatasemiconductormemorychipcanstoreiscalleditschipcapacity.ItcanbeinunitsofKbitskilobitsMbitsmegabitsandsoon.Thismustbedistinguishedfromthestoragecapacityofcomputers.WhilethememorycapacityofamemoryICchipisalwaysgiveninbitsthememorycapacityofacomputerisgiveninbytes.
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1.2MemoryorganizationMemorychipsareorganizedintoanumberoflocationswithintheIC.Eachlocationcanhold1bit4bits8bitsoreven16bitsdependingonhowitisdesignedinternally.Thenumberofbitsthateachlocationwithinthememorychipcanholdisalwaysequaltothenumberofdatapinsonthechip.How__nylocationsexistsinsideamemorychipdependsonthenumberofaddresspins.ThenumberoflocationswithinamemoryICalwaysequals2xwherexisthenumberofaddresspins.Thereforethetotalnumberofbitsthatamemorychipcanstoreisequaltothenumberoflocationstimesthenumberofdatabitperlocation.Tosum__ry:1Eachmemorychipcontains2xlocationswherexisthenumberofaddresspinsonthechip.2Eachlocationcontainsybitswhereyisthenumberofdatapinsonthechip.3Theentirechipwillcontain2x×ybitswherexisthenumberofaddresspinsonthechipandyisthenumberofdatapinsonthechip.4The2x×yisreferredtoastheorganizationofthememorychipwherexisthenumberofaddresspinsonthechipandyisthenumberofdatapinsonthechip.5For2xuse表6‑1togivethenumberoflocationsinKorMunits.表6‑1Powersof2x2x101K112K124K138K1416K1532K1664K17128K18256K19512K201M212M224M238M2416M324GExample1Agivenmemorychiphas12addresspinsand8datapins.Find:1theorganization2thecapacitySolution:1Thismemorychiphas4096locations212=4096andeachlocationcanhold8bitsofdata.Thisorganizationof4096×8oftenrepresentedas4K×
8.2Thecapacityisequalto32Kbitssin__thereisatotalof4Klocationsandeachlocationscanhold8bitsofdata.Example2A512Kmemorychiphas8pinsfordata.Find:1theorganization2thenumberofaddresspinsforthismemorychipSolution:1Amemorychipwith8datapinsmeansthateachlocationwithinthechipcanhold8bitsofdata.Tofindthenumberoflocationswithinthismemorychipdividethecapacitybythenumberofdatapins.512K/8=64K;thereforetheorganizationforthismemorychipis64K×
8.2Thischiphas16addresslinessin__216=64K.
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1.3SpeedOneofthemostimportantcharacteristicsofamemorychipisthespeedatwhichdatacanbeac__ssedfromit.Toac__ssthedatatheaddressispresentedtotheaddresspinsandaftera__rtainamountoftimehaselapsedthedatashowupatthedatapins.Theshorterthiselapsedtimethebetterandconsequentlythemoreexpensivethememorychip.Thespeedofthememorychipiscommonlyreferredtoasitsac__sstime.Theac__sstimeofmemorychipsvariesfromafewnanosecondstohundredsofnanosecondsdependingontheICtechnologyusedinthedesignandfabrication.
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1.4ROMread-onlymemoryROMisatypeofmemorythatdoesnotloseitscontentswhenthepoweristurnedoff.ForthisreasonROMisalsocallednonvolatilememory.Therearedifferenttypesofread-onlymemorysuchasPROMEPROMEEPROMflashROMand__skROM.
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1.5PROMprogram__bleROMorOTPROMPROMisreferredtothekindofROMthattheusercanburninfor__tionintoPROMisauser-program__blememory.ForeverybitofthePROMthereexistsafuse.PROMisprogrammedbyblowingthefusesblowafuse使保险丝熔断.Iftheinfor__tionburnedintoPROMiswrongPROMmustbediscardedsin__internalfusesareblownper__nently.ForthisreasonPROMisalsoreferredtoasOTPone-timeprogram__ble.Thepro__ssofprogrammingROMisalsocalledburningROMandrequiresspecialequipmentcalledaROMburnerorROMprogrammer.
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1.6EPROMerasableprogram__bleROMEPROMwasinventedtoallowchangesinthecontentsofPROMafteritisburned.InEPROMonecanprogramthememorychipanderaseitthousandsoftimes.AllEPROMchiph__eawindowthatisusedtoshineultr__ioletUV紫外线radiationtoeraseitscontents.TheonlyproblemwithEPROMisthaterasingitscontentscantakeupto20minutes.EPROMisalsoreferredtoasUV-erasableEPROMorsimplyUV-EPROM.The__jordisadvantageofUV-EPROMisthatitcannotbeprogrammedwhileinthesystemboardmotherboard.
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1.7EEPROMelectricallyerasableprogram__bleROMEEPROMhasseveraladvantagesoverEPROMsuchasthefactthatitsmethodoferasureiselectricalandthereforeinstant.
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1.8FlashmemorySin__theearly1990sflashROMhasbecomeapopularuser-program__blememorychip.Thepro__ssoferasureoftheentirecontentstakesonlyafewsecondsoronemightsayinaflashhen__itsname:Flashmemory.TheerasuremethodiselectricalandforthisreasonitissometimesreferredtoasFlashEEPROM.To__oidconfusionitiscommonlycalledFlashROM.The__jordifferen__betweenEEPROMandFlashmemoryisthefactthatwhenflashmemory’scontentsareerasedtheentiredevi__iserasedincontrasttoEEPROMwhereonecaneraseadesiredsectionorbyte.Althoughtherearesomeflashmemoriesre__ntly__de__ailableinwhichthecontentsaredividedintoblocksandtheerasurecanbedonebyblockunlikeEEPROMnobyteerasureoptionis__ailable.Somedesignersbelievethatflashmemorywillrepla__theharddiskas__ssstoragemedium.Thiswouldincreasetheperfor__n__ofcomputerstremendouslysin__flashmemoryissemiconductormemorywithac__ssrangeoftensofmilliseconds.Forthistohappenflashmemory’sprogram/erasecyclesmustbecomeinfinitejustlikeharddisks.Program/erasecyclereferstothenumberoftimesthatachipcanbeerasedandprogrammedbeforeitbecomesunusable.Atthistimetheprogram/erasecycleis500000forflashandEEPROM2000forUV-EPROMandinfiniteforRAManddisks.表6‑2ExamplesofROMmemorychipsTypePartNumberSpeednsCapacityOrganizationPinsVppUV-EPROM271645016K2K×824252716-135016K2K×824252716B45016K2K×
82412.52732A-4545032K4K×824212732A-2020032K4K×8242127C3245032K4K×824252764A-2525064K8K×
82812.527C64-1515064K8K×
82812.527128-20200128K16K×
82812.527C128-25250128K16K×
82812.527256-20200256K32K×
82812.527C256-20200256K32K×
82812.527512-25250512K64K×
82812.527C512-25250512K64K×
82812.527C010-121201M128K×
83212.527C201-121202M256K×
83212.527C410-121204M512K×
83212.5EEPROM28C16A-2525016K2K×82452864A25064K8K×828528C256-15150256K32K×828528C256-25250256K32K×8285FlashROM28F256-20200256K32K×8321228F256-15150256K32K×8321228F010-202001M128K×8321228F020-151502M256K×83212InpartnumbersCreferredtoCMOStechnologywhere27xxisforUV-EPROM28xxforEEPROM.27641282345678910272615PGMVppA12A7A6A51112131416171819202122232425A4A3A2A1A0O0O1O2GNDVccN.C.A8A9A11A10O7O6O5O4O3OECEA7A6A5A4A3A2A1A0O0O1O2GNDA7A6A5A4A3A2A1A0O0O1O2GNDVppA12A7A6A5A4A3A2A1A0O0O1O2GNDVppA12A7A6A5A4A3A2A1A0O0O1O2GNDVccA8A9A11/VppA10O7O6O5O4O3OECEVccA8A9VppA10O7O6O5O4O3OEVccA13A8A9A11A10O7O6O5O4O3PGMCECEOEVccA14A13A8A9A11A10O7O6O5O4O3OECE272562732A27128271627162732A2712827256图6‑161162Kx8SRAM
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1.9__skROM__skROMreferredtoakindofROMwhosecontentsareprogrammedbytheIC__nufacturer.Inotherworditisnotuser-program__bleROM.Theterminology__skisusedinICfabrication.
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1.10RAMrandomac__ssmemoryRAMmemoryiscalledvolatilememorysin__cuttingoffpowertotheICwillmeanthelossofdata.TherethreetypesofRAM:staticRAMSRAMdynamicRAMDRAMNV-RAMnonvolatileRAM
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1.11SRAMstaticRAMStorage__llsinstaticRAMmemoryare__deofflip-flopsandthereforedonotrequirerefreshinginordertokeeptheirdata.Theproblemwiththeuseofflip-flopsforstorage__llsisthateach__llrequiresatleast6transistorstobuildandthe__llholdsonly1bitofdata.Inre__ntyearsthe__llsh__ebeen__deof4transistorswhichisstilltoo__ny.Theuseof4-transistor__llplustheuseCMOStechnologyhasgivenbirthtoahigh-capacitySRAMbutthecapacityofSRAMisfarbelowDRAM.SRAMsarewidelyusedforcachememory.61162Kx812423456789102322A8WEIO61112CS131415161718192021A7A6A5A4A3A2A1A0IO0IO1IO2GNDVccA9A10IO7IO5IO4IO3OE图6‑261162Kx8SRAMA0-A10areforaddressinputswhere11addresslinesgives2K.I/O0-I/O7arefordataI/Owhile8-bitdatalinesgivesanorganizationof2Kx
8.WEwriteenableisforwritingdataintoSRAMactive-low.OEoutputenableisforreadingdataoutofSRAMactive-lowCSchipselectisusedtoselectthememorychip.ThefollowingarestepstowritedataintoSRAM:1ProvidetheaddressestopinsA0-A
10.2ActivatetheCSpin.3__keWE=0whileOE=14ProvidethedatatopinsI/O0-I/O
7.5__keWE=1anddatawillbewrittenintoSRAMonthepositiveedgeoftheWEsignal.AddressDatavalidDataholdDatasetupCSDatainWE图6‑3MemorywritetimingforSRAMThefollowingarestepstoreaddatafromSRAM:1ProvidetheaddressestopinsA0-A
10.Thisisthestartoftheac__sstimetAA2ActivatetheCSpin.3WhileWE=1ahigh-to-lowpulseontheOEpinwillreadthedataoutofthechip.AddressDatavalidtAACSDataoutOEAddressvalidtRC图6‑4MemoryreadtimingforSRAMInthe6116SRAMtheac__sstimetAAismeasuredasthetimeelapsedfromthemounttheaddressisprovidedtotheaddresspinstothemomentthatthedatais__ailableatthedatapins.Thespeedforthe6116chipcanvaryfrom100nsto15ns.ThereadcycletimetRCisdefinedasminimumamountoftimerequiredtoreadonebyteofdata.Thatisfromthemomentweapplytheaddressesofthebytetothemomentwecanbeginthenextoperation.InSRAMforwhichtAA=100nstRCisalso100ns.Thisimpliesthatwecanreadthecontentsofconsecutiveaddresslocationswitheachtakingnomorethan100ns.Hen__inSRAMandROMtAA=tRC.TheyarenotequalinDRAM.
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1.12DRAMdynamicRAMSin__theearlydaysofthecomputertheneedforhugeinexpensiveread/writememorywasa__jorpreoccupation当务之急ofcomputerdesigners.In1970IntelCorporationintrodu__dthefirstdynamicRAM.Itsdensitycapacitywas1024bitsanditusedacapacitortostoreeachbit.Theuseofacapacitorasameanstostoredatacutsdownthenumberoftransistorsneededtobuildthe__ll;howeveritrequiresconstantrefreshingduetoleakage泄漏.The__joradvantagesofDRAMmemoryarehighdensitycapacitycheapercostperbitandlowerpowerconsumptionperbit.Thedisadvantageisthatitmustberefreshedperiodicallyduetothefactthatthecapacitor__lllosesitscharge;furthermorewhileitisbeingrefreshedthedatacannotbeac__ssed.Afterthe1K-bitchipcamethe4K-bitin1973andthenthe16Kchipin
1976.The1980ssawtheintroductionof64K256Kandfinally1Mand4Mmemorychip.The1990ssawthe16M64Mand256MDRAMchip.256Kx111623456781514WE910111213A8DINRASA0A2A1VCCGNDDOutA4A7A6CASA3A5图6‑5256Kx1DRAM
6.2MEMORYADDRESSINGDECODINGCurrentsystemdesignsuseCPLDscomplexprogram__blelogicdevi__sinwhichmemoryandaddressdecodingcircuitryareintegratedintooneprogram__blechip.Howeveritisimportanttounderstandhowthistaskcanbeperformedwithcommonlogicgates.
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2.1______logicgatesasaddressdecoderInconnectingamemorychiptotheCPUthedatabusisconnecteddirectlytothedatapinsofthememory.ControlsignalsMEMRandMEMWareconnectedtotheOEandWRpinsofthememorychiprespectively.InthecaseoftheaddressbuseswhilethelowerbitsoftheaddressgodirectlytothememorychipaddresspinstheupperonesareusedtoactivatetheCSsometimesthechipselectisalsoreferredtoasachipenable__pinofthememorychip.ItistheCSpinalongwithRD/WRthatallowstheflowofdatainoroutofthememorychip.TheCSinputisactivelowandcanbeactivatedusingsome______logicgatessuchasNANDandinverters.�1�32Kx8A0OEA140000D7D0WRCS1000000000000000A19MEMWMEMRA15A16A17A18A19A000001111111111111111=08000Haddressofthefirstlocation=0FFFFHaddressofthelastlocation图6‑6Using______logicgatesasdecoder�1�64Kx8A0OEA15D7D0WRCSMEMWMEMRA16A17A18A1910010000000000000000A19A010011111111111111111=90000Haddressofthefirstlocation=9FFFFHaddressofthelastlocation图6‑7Decoderanditsassociatedaddressrange
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2.2Usingthe74LS138asdecoder74LS138AG2BG1Y0G2AG1XLHHHHHHHHG2HXLLLLLLLLY1CXXLLLLHHHHBXXLLHHLLHHAXXLHLHLHLHY0HHLHHHHHHHBCY2Y3Y4Y5Y6Y7Y1HHHLHHHHHHY2HHHHLHHHHHY3HHHHHLHHHHY4HHHHHHLHHHY5HHHHHHHLHHY6HHHHHHHHLHY7HHHHHHHHHLEnableSelectOutputsInputsFunctionTableBlockDiagram图6‑874LS138decoderThe3inputsABandCofthe74LS138generate8active-lowoutputsY0-Y
7.EachYoutputisconnectedtotheCSofamemorychipallowingcontrolof8memoryblocksbyasingle74LS
138.G2AG2BandG1canbeusedforaddressorcontrolsignalselection.Noti__thatG2AandG2BarebothactivelowwhileG1isactivehigh.IfanyoneoftheinputsG1G2AandG2Bisnotconnectedtheymustbeactivatedper__nentlybyeitherVccorgrounddependingontheactivationlevel.74LS138AG2BG1Y0G2AY1Y2Y3Y4Y5Y6Y7BC64Kx8ROMA0OEA15D7D0CEVppMEMRVccA16A17A18A19AddressrangeC0000–CFFFFisassignedtoY4EachYcontrolsoneblock图6‑974LS138asdecoderExample:LookingatthedesigninthefollowingfigurefindtheaddressrangeforaY4bY2andcY7andverifytheblocksizecontrolledbyeachY.�1�74LS138AG2BG1Y0G2AY1Y2Y3Y4Y5Y6Y7BC16Kx8ROMA0OEA13D7D0CEMEMRVppVccA16A17A18A19EachYcontrolsoneblockA15A14图6‑1074LS138asdecoderSolution:aTheaddressrangeforY4iscalculatedasfollows:A19A18A17A16A15A14A13A12A11A10A9A8A7A6A5A4A3A2A1A01111000000000000000011110011111111111111TheaboveshowsthattherangeforY4isF0000HtoF3FFFH.Noti__thatA19A18andA17mustbe1forthedecodertobeactivated.Y4willbeselectedwhenA16A15andA14=100BA13-A0willbe0forthelowestaddressand1forthehighestaddress.bTheaddressrangeforY2isE8000HtoEBFFFHA19A18A17A16A15A14A13A12A11A10A9A8A7A6A5A4A3A2A1A01110100000000000000011101011111111111111cTheaddressrangeforY7isFC000HtoFFFFFHTheblocksizeis16K.
6.3存储器容量的扩展当使用一片ROM或RAM芯片不能满足容量要求时,需要将若干ROM或RAM组合起来
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3.1位扩展方式若一片ROM或RAM芯片中的字数(字节数量)已经够用,而每一个字的位数不够时,应采用位扩展的连接方式将多个ROM或RAM芯片组合成位数更多的存储器例用8片1024x1位的RAM连接成1024x8位的RAM1024Kx1A0A
1...A9WR/CSI/OI/O71024Kx1CSWR/A0A
1...A9I/OI/O1A01024Kx1CSWR/A0A
1...A9I/OI/O0…A1A9WR/CSD0D1D
7...………...图6‑
116.
3.2字扩展方式也称地址扩充若每一片ROM或RAM芯片中的数据位数已经够用,而每一个字数不够时,应采用字扩展的连接方式将多个ROM或RAM芯片组合成位数更多的存储器例用4片256x8位的RAM连接成1024x8位的RAM256Kx84CSWR/A
0...A7I/O0I/O
7...256Kx83CSWR/A
0...A7I/O0I/O
7...256Kx82CSWR/A
0...A7I/O0I/O
7...256Kx81CSWR/A
0...A7I/O0I/O
7...D0D7A0A9Y12:4译码Y0WR/...Y2Y2A8A
9...……………………图6‑12地址分配
(1)000H~0FFH
(2)100H~1FFH
(3)200H~2FFH
(4)300H~3FFH
6.4存储器与CPU的连接将存储芯片的引脚与系统总线相连接
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4.1数据线的连接按位扩展方式将芯片扩展到数据总线宽度,形成存储器模块(内存条)
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4.2地址线的连接存储芯片的地址通常应全部与系统的低位地址总线相连,寻址时这部分地址的译码是在芯片内部完成的,称为“片内译码”设某存储芯片有n根地址线,当该片被选中后,其地址线将输入n位地址,芯片内部进行n:2n的译码,译出的的地址范围为00…0n位到11…1n位
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4.3片选端的译码一个存储芯片(组)很难满足存储系统的要求,常利用地址扩展的方式将多个存储芯片(组)__起来将存储芯片的片选端与系统的高位地址线相关联,当高位地址满足一定条件时才会选中某个指定的芯片(组)具体的方法有全译码,使用系统的全部高位地址线参加对芯片(组)的译码寻址部分译码,只使用系统的部分高位地址线参加对芯片(组)的译码寻址线选译码,仅使用某一高位地址线选中某个芯片(组)
6.
4.
3.1全译码所有系统地址线均参与对存储单元的译码寻址低位地址线对芯片内各存储单元译码寻址,片内译码高位地址线对芯片译码寻址,片选译码每个存储单元的地址都是唯一的,不存在地址重复,但译码电路可能比较复杂,连线也较多74LS138AG2BG1Y0G2AY1Y2Y3Y4Y5Y6Y7BCCE1A13A14A15A16A17A18A19IOM/27648Kx8A12~A0图6‑13该片2764的地址范围是A19A18A17A16A15A14A13A12A11A10A9A8A7A6A5A4A3A2A1A0000111000000000000001C000000111011111111111111DFFF
6.
4.
3.2部分译码只有部分高地址线参与片选译码对于那些未参与译码的高地址可以为1也可以为0,因此每个存储单元将对应多个地址,造成地址重复,需要选取其中的一个可用地址采用部分译码可以简化译码电路的设计,但是由于地址重复,系统地一部分地址空间资源被浪费一般应安排最高地址线不参与译码74LS138AG2BG1Y0G2AY1Y2Y3Y4Y5Y6Y7BC27324Kx8127324Kx8227324Kx8327324Kx84CECECECE1IOM/A12A13A14A17A16A0A11图6‑14芯片A19A18A17A16A15A14A13A12A11A10A9A8A7A6A5A4A3A2A1A01xx10x0000000000000001111111111112xx10x0010000000000001111111111113xx10x0100000000000001111111111114xx10x
0110000000000001111111111116.
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3.3线选译码只用少数几根高位地址线进行芯片的译码,且每根负责选中一个芯片(组)构成简单,但地址空间浪费严重27648Kx8127648Kx82CECEA0A12A13A14图6‑15芯片A19A18A17A16A15A14A13A12A11A10A9A8A7A6A5A4A3A2A1A01xxxxx10000000000000011111111111112xxxxx
01000000000000011111111111116.
4.4读写控制-OE与系统的控制总线中的-MEMR或-RD相连当芯片被选中、且读命令有效时,存储芯片将选中单元的数据送出到数据总线-WE与系统的控制总线中的-MEMW或-WR相连当芯片被选中、且写命令有效时,允许总线数据写入存储芯片指定的单元最后,分析下图所示存储器连接的一个综合性实例图6‑16图中,存储器由两类芯片构成,RAM采用两片Intel6264芯片(8K×8);EPROM采用两片Intel2732(4K×8),构成16KB的RAM和8KB的ROM采用部分译码方式4块芯片各自所需的片__址线及形成的片间地址线分析如下选择A
15、A
14、A13作为3:8译码器的三个数据输入(C、B、A),选择A
17、A16做3:8译码器门控__,3:8译码器的Y
0、Y1分别连接2片6264芯片的片选__线CS1,3:8译码器的Y2及A12组合后产生的__分别连接2片2732芯片的片选__线__这样实例中各芯片的内存地址为芯片A19A18A17A16A15A14A13A12A11A10A9A8A7A6A5A4A3A2A1A
06264.1xx
00000000000000000011111111111116264.2xx
00001000000000000011111111111112732.1xx
0001000000000000001111111111112732.2xx000101000000000000111111111111有4个重叠区A
19、A18=00时6264的1号芯片地址从00000-01FFF,2号芯片地址从02000H-03FFFH2732的1号芯片地址从04000-04FFF,2号芯片地址从05000H-05FFFHA
19、A18=01时6264的1号芯片地址从40000H-41FFFH,2号芯片地址从42000H-43FFFH2732的1号芯片地址从44000H-44FFFH,2号芯片地址从45000H-45FFFHA
19、A18=10时6264的1号芯片地址从80000H-81FFFH,2号芯片地址从82000H-83FFFH2732的1号芯片地址从84000H-84FFFH,2号芯片地址从85000H-85FFFHA
19、A18=11时6264的1号芯片地址从0C0000-0C1FFF,2号芯片地址从0C2000-0C3FFF2732的1号芯片地址从0C4000-0C4FFF,2号芯片地址从0C5000-0C5FFFIntel8088CPU需扩展存储器4Kx8ROM,选用2Kx8的Intel2716;以及扩展1Kx8RAM,选用1Kx4的Intel2___,要求ROM地址空间从1000H开始,RAM地址空间从3000H开始1)CPU与74LS138的连线2)74LS138与存储器的片选__的连线3)Intel2___和Intel2716与CPU的连线4)各个芯片的地址范围AD7AD6AD5AD4AD3AD2AD1AD0A8A9A10A11A12A13A14A15RDWR8088ALE768910111213141516251D2D3D4D5D6D7D8DC1Q2Q3Q4Q5Q6Q7Q8Q1916151296521615171234765A0A1A2A3A4A5A6A7A8A9I/O1I/O2I/O3I/O4CSIntel21141811121314WE10Intel211411615171234765A0A1A2A3A4A5A6A7A8A9I/O1I/O2I/O3I/O4CS11121314WE10Intel271612219231234567A1A2A3A4A5A6A7A8A9A10A0O0O1O2CEO3O4O5O6O78910111314151617OE20818Intel271622219231234567A1A2A3A4A5A6A7A8A9A10CEA0O0O1O2O3O4O5O6O78910111314151617OE201874LS138AG2BG1Y0G2AY1Y2Y3Y4Y5Y6Y7BC1236451514131211109774LS373D0D1D2D3D4D5D6D73229543239
6.5IBMPCMEMORY__PFFFFFFFF4GHighMemoryArea386/486/Pentium9FFFF0FFFFF1MA000010000010FFEFFFFFFF16M286ExtendedMemory扩展内存UpperMemoryArea高端内存区ConventionalMemory常规内存图6‑
176.616位和32位微机系统的内存__
6.
6.116位微机系统的内存__8086用20位地址总线寻址1MB存储空间,由两个存储体组成奇地址存储体偶地址存储体16位CPU对存储器的访问分为按字节访问按字访问图6‑
186.
6.232位微机系统的内存__图6‑19。