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IS戋女岑本科生毕业设计(论文)外文翻译毕业设计题目夕卜文题目FundamentalsofSingIe-chipMicrocomputer译文题目单片机基础学院信息科学与工程学院专业班级电子信息工程0802班学生闻家音指导教师朱建光外文原文FundamentalsofSingIe-chipMicrocomputerDr.DobbsMacintoshJournaIAbstractThesingle-chipmicrocomputeristheculminationofboththedeveIopmentofthedigitalcomputerandtheintegratedcircuitarguabIythetowmostsignificantinventionsofthe20thcentury.ThesetowtypesofarchitecturearefoundinsingIe-chipmicrocomputer.SomeempIoythesplitprogram/datamemoryoftheHarvardarchitectureshowninFig.3-5A-1othersfoIIowthephiIosophywidelyadaptedforgeneraI-purposecomputersandmicroprocessorsofmakingnologicaldistinctionbetweenprogramanddatamemoryasinthePrincetonarchitecture.IngeneraItermsasingle-chipmicrocomputerischaracterizedbytheincorporationofaIItheunitsofacomputerintoasingledevice.Keyword:Single-chipMicrocomputerROMRAMProgrammingAlgorithmFeaturesCompatibIewithMCS-51™Products4KBytesofIn-SystemReprogrammabIeFIashMemory-Endurance:1000Write/EraseCycIesFullyStaticOperation0Hzto24MHzThree-1eveIProgramMemoryLock128x8-bitInternaIRAM32ProgrammabIeI/OLinesTwo16-bitTimer/CountersSixInterruptSourcesProgrammabIeSeriaIChanneI•Low-powerIdleandPower-downModesDescriptionTheAT89C51isaIow-powerhigh-performanceCMOS8-bitmicrocomputerwith4KbytesofFIashprogrammabIeanderasabIereadonIymemoryPEROM.ThedeviceismanufacturedusingAtmeIshigh-densitynonvoIatiIememorytechnoIogyandiscompatibIewiththeindustry-standardMCS-51instructionsetandpinout.Theon-chipFIashaIIowstheprogrammemorytobereprogrammedin-systemorbyaconventionaInonvoIatiIememoryprogrammer.BycombiningaversatiIe8-bitCPUwithFIashonamonoIithicchiptheAtmeIAT89C51isapowerfuImicrocomputerwhichprovidesahighIy-fIexibIeandcost-effectivesoIutiontomanyembeddedcontroIappIications.TheAT89C51providesthefoIlowingstandardfeatures:4KbytesofFlash128bytesofRAM32I/OIinestwo16-bittimer/countersafivevectortwo-1eveIinterruptarchitectureafuIIdupIexseriaIporton-chiposciIIatorandcIockcircuitry.InadditiontheAT89C51isdesignedwithstaticIogicforoperationdowntozerofrequencyandsupportstwosoftwareseIectabIepowersavingmodes.TheIdleModestopstheCPUwhileallowingtheRAMtimer/countersserialportandinterruptsystemtocontinuefunctioning.ThePower-downModesavestheRAMcontentsbutfreezestheosciIIatordisabIingaIIotherchipfunctionsuntiIthenexthardwarereset.PinConfigurationsPQFP/TQFPP
1.0•Pl.7PinDescriptionVCCSuppIyvoItage.GNDGround.Port0Port0isan8-bitopen-drainbi-directionaII/Oport.AsanoutputporteachpincansinkeightTTLinputs.When1sarewrittentoport0pinsthepinscanbeusedashighimpedanceinputs.Port0mayaIsobeconfiguredtobethemu11ipIexedIoworderaddress/databusduringaccessestoexternaIprogramanddatamemory.InthismodePOhasinternaIpuIIups.Port0aIsoreceivesthecodebytesduringFIashprogrammingandoutputsthecodebytesduringprogramverification.ExternaIpuIIupsarerequiredduringprogramverification.Port1toPort2pinstheyarepulledhighbytheinternaIpuIIupsandasinputs.AsinputsPort2pinsthatareexternaIIybeingpulledIowwiIIsourcecurrentIILbecauseoftheinternaIpuIIups.Port2emitsthehigh-orderaddressbyteduringfetchesfromexternaIprogrammemoryandduringaccessestoexternaIdatamemorythatuse16~bitaddressesMOVXDPTR.InthisappIicationitusesstronginternaIpuIIupswhenemitting1s.DuringaccessestoexternaIdatamemorythatuse8-bitaddressesMOVXRIPort2emitsthecontentsoftheP2SpecialFunctionRegister.Port2aIsoreceivesthehigh-orderaddressbitsandsomecontrolsignaIsduringFIashprogrammingandverification.Port3Port3isan8-bitbi~directionaII/OportwithinternaIpuIIups.ThePort3outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort3pinstheyarepulledhighbytheinternaIpuIIupsandcanbeusedasinputs.AsinputsPort3pinsthatareexternaIIybeingpulledlowwiIIsourcecurrentIILbecauseofthepuIIups.Port3aIsoservesthefunctionsofvariousspeciaIfeaturesoftheAT89C51asIistedbelow:Port3aIsoreceivessomecontroIsignaIsforFIashprogrammingandverification.ALE/PROGAddressLatchEnabIeoutputpuIseforIatchingtheIowbyteoftheaddressduringaccessestoexternaImemory.ThispinisaIsotheprogrampuIseinputPROGduringFIashprogramming.InnormaIoperationALEisemittedataconstantrateof1/6theosciIIatorfrequencyandmaybeusedforexternaItimingorcIockingpurposes.NotehoweverthatoneALEpuIseisskippedduringeachaccesstoexternaIDataMemory.IfdesiredALEoperationcanbedisabIedbysettingbit0ofSFRIocation8EH.WiththebitsetALEisactiveonIyduringaMOVXorMOVCinstruction.OtherwisethepinisweakIypulledhigh.SettingtheALE-disabIebithasnoeffectifthemicrocontrollerisinexternaIexecutionmode.PSENProgramStoreEnabIeisthereadstrobetoexternaIprogrammemory.WhentheAT89C51isexecutingcodefromexternaIprogrammemoryPSENisactivatedtwiceeachmachinecycIeexceptthattwoPSENactivationsareskippedduringeachaccesstoexternaIdatamemory.EA/VPPExternaIAccessEnabIe.EAmustbestrappedtoGNDinordertoenabIethedevicetofetchcodefromexternaIprogrammemoryIocationsstartingat0000HuptoFFFFH.NotehoweverthatifIockbit1isprogrammedEAwillbeinternaIIyIatchedonreset.EAshouIdbestrappedtoVCCforinternaIprogramexecutions.ThispinaIsoreceivesthe12-voltprogrammingenabIevoltageVPPduringFIashprogrammingforpartsthatrequire12-voltVPP.XTAL1InputtotheinvertingosciIIatorampIifierandinputtotheinternaIcIockoperatingcircuit.XTAL2OutputfromtheinvertingosciIIatoramplifier.Osci11atorCharacteristiesXTAL1andXTAL2aretheinputandoutputrespectiveIyofaninvertingampIifierwhichcanbeconfiguredforuseasanon-chiposciIIatorasshowninFigure
1.EitheraquartzerystaIorceramicresonatormaybeused.TodrivethedevicefromanexternaIcIocksourceXTAL2shouIdbeIeftunconnectedwhileXTAL1isdrivenasshowninFigure
2.TherearenorequirementsonthedutyeyeIeoftheexternaIcIocksignaIsineetheinputtotheinternaIcIockingcircuitryisthroughadivide-by-twofIip-fIopbutminimumandmaximumvoItagehighandIowtimespecificationsmustbeobserved.IdleModeInidlemodetheCPUputsitseIftosIeepwhileaIItheonchipperipheraIsremainactive.Themodeisinvokedbysoftware.Thecontentoftheon-chipRAMandaIIthespeciaIfunctionsregistersremainunchangedduringthismode.TheidlemodecanbeterminatedbyanyenabIedinterruptorbyahardwarereset.ItshouIdbenotedthatwhenidleisterminatedbyahardwareresetthedevicenormaIIyresumesprogramexecutionfromwhereitIeftoffuptotwomachineeyeIesbeforetheinternaIresetaIgorithmtakescontroI.On-chiphardwareinhibitsaccesstointernaIRAMinthiseventbutaccesstotheportpinsisnotinhibited.ToeIiminatethepossibiIityofanunexpectedwritetoaportpinwhenIdleisterminatedbyresettheinstructionfollowingtheonethatinvokesIdIeshouIdnotbeonethatwritestoaportpinortoexternaImemory.Figure
1.OsciIIatorConnectionsC2口5TIIA-X7AL2X7AL1GNDNote:C1C2=30pF±10pFforCrystals=40pF±10pFforCeramicResonatorsFigure
2.ExternaIClockDriveConfigurationNCEXTERNALOSCILLATORSIGNALPower-downModeXTAL2X7AL1GNDInthepower-downmodetheosciIIatorisstoppedandtheinstructionthatinvokespower-downistheIastinstructionexecuted.Theon-chipRAMandSpeciaIFunctionRegistersretaintheirvaIuesuntiIthepower-downmodeisterminated.TheonIyexitfrompower-downisahardwarereset.ResetredefinestheSFRsbutdoesnotchangetheon-chipRAM.TheresetshouIdnotbeactivatedbeforeVCCisrestoredtoitsnormaIoperatingIeveIandmustbeheIdactiveIongenoughtoaIIowtheosciIIatortorestartandstabiIize.StatusofExternalPinsDuringIdleandPower-downModesProgramMemoryLockBitsOnthechiparethreeIockbitswhichcanbeIeftunprogrammedUorcanbeprogrammedPtoobtaintheadditionalfeaturesIistedinthetabIebeIow.Whenlockbit1isprogrammedthelogicIeveIattheEApinissampledandIatchedduringreset.IfthedeviceispoweredupwithoutaresettheIatchinitializestoarandomvaIueandhoIdsthatvaIueuntiIresetisactivated.11isnecessarythattheIatchedvaIueofEAbeinagreementwiththecurrentlogicIeveIatthatpininorderforthedevicetofunctionproperIy.LockBitProtectionModesProgrammingtheFlashTheAT89C51isnormaIIyshippedwiththeon-chipFIashmemoryarrayintheerasedstatethatiscontents二FFHandreadytobeprogrammed.Theprogramminginterfaceacceptseitherahigh-voltage12-voltoralow-voltageVCCprogramenabIesignaI.TheIow~voItageprogrammingmodeprovidesaconvenientwaytoprogramtheAT89C51insidetheuserssystemwhilethehigh-voItageprogrammingmodeiscompatibIewithconventionaIthirdpartyFIashorEPROMprogrammers.TheAT89C51isshippedwitheitherthehigh-voltageorIow~voItageprogrammingmodeenabIed.Therespectivetop-sidemarkinganddevicesignaturecodesareIistedinthefoIlowingtabIe.TheAT89C51codememoryarrayisprogrammedbyte-bybyteineitherprogrammingmode.Toprogramanynonb/ankbyteintheon-chipFlashMemorytheentirememorymustbeerasedus/ngtheChipEraseMode.ProgrammingAlgorithm:BeforeprogrammingtheAT89C51theaddressdataandcontroIsignaIsshouIdbesetupaccordingtotheFIashprogrammingmodetabIeandFigure3andFigure
4.ToprogramtheAT89C51takethefoIlowingsteps.InputthedesiredmemoryIocationontheaddressIines.InputtheappropriatedatabyteonthedataIines.ActivatethecorrectcombinationofcontroIsignaIs.RaiseEA/VPPto12Vforthehigh-voltageprogrammingmode.PuIseALE/PROGoncetoprogramabyteintheFlasharrayortheIockbits.Thebyte-writeeyeIeisseIf-timedandtypicaIIytakesnomorethan
1.5ms.Repeatsteps1through5changingtheaddressanddatafortheentirearrayoruntiItheendoftheobjectfileisreached.DataPolIing:TheAT89C51featuresDataPoIIingtoindicatetheendofawriteeyeIe.DuringawriteeyeIeanattemptedreadoftheIastbytewrittenwiIIresultinthecompIementofthewrittendatumonPO.
7.OncethewriteeyeIehasbeencompIetedtruedataarevalidonaIIoutputsandthenexteyeIemaybegin.DataPollingmaybeginanytimeafterawriteeyeIehasbeeninitiated.Ready/Busy:TheprogressofbyteprogrammingcanaIsobemonitoredbytheRDY/BSYoutputsignaI•P
3.4ispulIedIowafterALEgoeshighduringprogrammingtoindicateBUSY.P
3.4ispulledhighagainwhenprogrammingisdonetoindicateREADY.ProgramVerify:IflockbitsLB1andLB2havenotbeenprogrammedtheprogrammedcodedatacanbereadbackviatheaddressanddataIinesforverification.TheIockbitscannotbeverifieddirectIy.VerificationoftheIockbitsisachievedbyobservingthattheirfeaturesareenabIed.ChipErase:TheentireFlasharrayiserasedeIectricaIIybyusingthepropercombinationofcontrolsignaIsandbyholdingALE/PROGIowfor10ms.ThecodearrayiswrittenwithaII“1s.Thechiperaseoperationmustbeexecutedbeforethecodememorycanbere-programmed.ReadingtheSignatureBytes:ThesignaturebytesarereadbythesameprocedureasanormaIverificationofIocations030H031Hand032HexceptthatP
3.6andP
3.7mustbepulledtoalogiclow.ThevaIuesreturnedareasfOllOWSe030H=1EHindicatesmanufacturedbyAtmeI031H二51Hindicates89C51032H二FFHindicates12Vprogramming032H二05Hindicates5VprogrammingFlashProgrammingModesNote:
1.ChipEraserequiresa10msPROGpulse.ProgrammingInterfaceEverycodebyteintheFIasharraycanbewrittenandtheentirearraycanbeerasedbyusingtheappropriatecombinationofcontroIsignaIs.ThewriteoperationeyeIeisseIftimedandonceinitiatedwiIIautomaticaIIytimeitselftocompIetion.AlImajorprogrammingvendorsofferworIdwidesupportfortheAtmeImicrocontrollerseries.PleasecontactyourIocaIprogrammingvendorfortheappropriatesoftwarerevision.AbsoluteMaximumRatings*OperatingTemperature-55°Cto+125°CStorageTemperature-65°Cto+150°CVoltageonAnyPinwithRespecttoGround-
1.0Vto+
7.0VMaximumOperatingVoltage
6.6VDCOutputCurrent
15.0mA外文资料翻译译文单片机基础摘要单片机是电脑和集成电路发展的巅峰,有据可查的是它们也是20世纪最意义的两大发明这两种特性在单片机中得到了充分的体现一些厂家用这两种特性区分程序存储器和数据存储器在硬件中的特性,依据同样的原理广泛的适用于一般目的的电脑和微电脑,一些厂家在程序存和数据存之间不区分,像普林斯顿特性关键字单片机只读存贮器随机存取存储器编程方法AT89C51主要性能参数与MCS-51产品指令系统完全兼容4K字节可重榛写Flash闪速存储器1000次擦写周期全静态操作0HZ-24MHZ三级加密程序存储器128*8字节部RAM32个可编程I/O口线2个16位定时/记数器6个中断源可编程串行UART通道低功耗空闲和掉电模式功能特性概述AT89C51提供以下标准功能4K字节Flash闪速存储器,128字节部RAM32个I/O口线,两个16位定时/记数器,一个5向量两级中断结构,一个全双工串行通信口,片振荡器与时钟电路同时,AT89C51可降至OHZ的静态逻辑操作,并支持两种软件可选的节电工作模式空闲方式停止CPU的工作,但允许RAM定时/记数器,串行通信口与中断系统继续工作掉电方式保存RAM中的容,但振荡器停止工作直到下一个硬件复位AT89C51是美国ATMEL公司生产的低电压,高性能CM0S8位单片机,片含4kbytes的可反复擦写的只读程序存储器PEROM和128bytes的随机存取数据存储器RAM器件采用ATMEL公司的高密度、非易失性存储技术生产,兼容标准MCS-51指令系统片置通用8位中央处理器CPU和Flash存储单元,功能强大AT89C51单片机可为您提供许多高性价比的应用场合,可灵活应用于各种控制领域PDIPP
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1.7T;TIFLASHBUFFERPCPROGRAMCOUNTERPROGRAMADDRESSREGISTER引脚功能说明Vcc:电源电压GND:地P0口P0口是一组8位漏极开路型双向I/O口,也即地址/数据总线复用口作为输出口用时,每位能吸收电流的方式驱动8个TTL逻辑门电路,对端口写“1可作为高阻抗输入端用在访问外部数据存储器或程序存储器时,这组口线分时转换地址(低8位)和数据总线复用,在访问期间激活部上拉电阻在Flash编程时,P0口接收指令字节,而在程序校验时,输出指令字节,校验时,要求外接上拉电阻•P1口P1是一个带部上拉电阻的8位双向I/O口,P1的输出缓冲级可驱动(吸收或输出电流)4个TTL逻辑门电路对端口写“1”,通过部的上拉电阻把端口拉到高电平,此时可作输入口作输入口使用时,因为部存在上拉电阻,某个引脚被外部信号拉低时会输出一个电流(IIL)oFlash编程和程序校验期间,P1接收低8位地址•P2口P2是一个带有部上拉电阻的8位双向I/O口,P2的输出缓冲级可驱动(吸收或输出电流)4个TTL逻辑门电路对端口写“1”,通过部的上拉电阻把端口拉到高电平,此时可作输入口,作输入口使用时,因为部存在上拉电阻,某个引脚被外部信号拉低时会输出一个电流(HL)o在访问外部程序存储器或16位地址的外部数据存储器(例如执行MOVXDPTR指令)时,P2口送出高8位地址数据在访问8位地址的外部数据存储器(如执行MOVXRI指令)时,P2口线上的容(也即特殊功能寄存器(SFR)区中R2寄存器的容),在整个访问期间不改变Flash编程或校验时,P2亦接收高位地址和其它控制信号•P3口P3口是一组带有部上拉电阻的8位双向I/O口P3口输出缓冲级可驱动(吸收或输出电流)4个TTL逻辑门电路对P3口写入“1”时,它们被部上拉电阻拉高并可作为输入端口作输入端时,被外部拉低的P3口将用上拉电阻输出电流(IIL)oP3口除了作为一般的I/0口线外,更重要的用途是它的第二功能,如下表所示P3口还接收一些用于Flash闪速存储器编程和程序校验的控制信号-RST复位输入当振荡器工作时,RST引脚出现两个机器周期以上高电平将使单片机复位-ALE/PROG:当访问外部程序存储器或数据存储器时,ALE(地址锁存允许)输出脉冲用于锁存地址的低8位字节即使不访问外部存储器,ALE仍以时钟振荡频率的1/6输出固定的正脉冲信号,因此它可对外输出时钟或用于定时目的要注意的是每当访问外部数据存储器时将跳过一个ALE脉冲对Flash存储器编程期间,该引脚还用于输入编程脉冲(PROG)o如有必要,可通过对特殊功能寄存器(SFR)区中的8EH单元的DO位置位,可禁止ALE操作该位置位后,只有一条MOVX和MOVC指令ALE才会被激活此外,该引脚会被微弱拉高,单片机执行外部程序时应设置ALE无效-PSEN:程序储存允许(PSEN)输出是外部程序存储器的读选通信号,当AT89C51由外部程序存储器取指令(或数据)时,每个机器周期两次PSEN有效,即输出两个脉冲在此期间,当访问外部数据存储器,这两次有效的PSEN信号出现•EA/VPP:外部访问允许欲使CPU仅访问外部程序存储器(地址为0000H—FFFFH)EA端必须保持低电平(接地)需注意的是如果加密位LB1被编程,复位时部会锁存EA端状态如EA端为高电平(接VCC端),CPU则执行部程序存储器中的指令Flash存储器编程时,该引脚加上+12V的编程允许电源Vpp当然这必须是该器件是使用12V编程电压Vppo-XTAL1:振荡器反相放大器的与部时钟发生器的输入端-XTAL2振荡器反相放大器的输出端•时钟振荡器AT89C51中有一个用于构成部振荡器的高增益反相放大器,引脚XTAL1和XTAL2分别是该放大器的输入端和输出端这个放大器与作为反馈元件的片外石英晶体或瓷谐振器一起构成自激振荡器,振荡电路参见图5外接石英晶体(或瓷谐振器)与电容C
1、C2接在放大器的反馈回路中构成并联振荡电路对外接电容C
1、C2虽然没有十分严格的要求,但电容容量的大小会轻微影响振荡频率的高低、振荡器工作的稳定性、起振的难易程序与温度稳定性,如果使用石英晶体,我们推荐电容使用30pF±10pF而如使用瓷谐振器建议选择40pF±10Fo用户也可以采用外部时钟采用外部时钟的电路如图5右图所示这种情况下,外部时钟脉冲接到XTAL1端,即部时钟发生器的输入端,XTAL2则悬空X7AL1GND图1石英晶体时C1C2=30pF±10pF瓷滤波器C1C2=40pF±10pF部振荡电路X1AL2EXTERNALOSCILLATORSIGNALGND图2外部时钟驱动电路由于外部时钟信号是通过一个2分频触发器后作为部时钟信号的,所以对外部时钟信号的占空比没有特殊要求,但最小高电平持续时间和最大的低电平持续时间应符合产品技术条件的要求-空闲节电模式AT89C51有两种可用软件编程的省电模式,它们是空闲模式和掉电工作模式这两种方式是控制专用寄存器PC0N即电源控制寄存器中的PDPC0N.1和IDLPC0N.0位来实现的PD是掉电模式,当PDH时,激活掉电工作模式,单片机进入掉电工作状态IDL是空闲等待方式,当IDL二1激活空闲工作模式,单片机进入睡眠状态如需同时进入两种工作模式,即PD和IDL同时为1则先激活掉电模式在空闲工作模式状态,CPU保持睡眠状态而所有片的外设仍保持激活状态,这种方式由软件产生此时,片RAM和所有特殊功能寄存器的容保持不变空闲模式可由任何允许的中断请求或硬件复位终止终止空闲工作模式的方法有两种,其一是任何一条被允许中断的事件被激活,IDL(PCON.0)被硬件清除,即刻终止空闲工作模式程序会首先响应中断,进入中断服务程序,执行完中断服务程序并紧随RETI(中断返回)指令后,下一条要执行的指令就是使单片机进入空闲模式那条指令后面的一条指令其二是通过硬件复位也可将空闲工作模式终止需要注意的是,当由硬件复位来终止空闲工作模式时,CPU通常是从激活空闲模式那条指令的下一条指令开始继续执行程序的,要完成部复位操作,硬件复位脉冲要保持两个机器周期(24个时钟周期)有周在这种情况下,部禁止CPU访问片RAM而允许访问其它端口为了避免可能对端口产生意外写入,激活空闲模式的那条指令后一条指令不应是一条对端口或外部存储器的写入指令-掉电模式在掉电模式下,振荡器停止工作,进入掉电模式的指令是最后一条被执行的指令,片RAM和特殊功能寄存器的容在终止掉电模式前被冻结退出掉电模式的唯一方法是硬件复位,复位后将重新定义全部特殊功能寄存器但不改变RAM中的容在Vcc恢复到正常工作电平前,复位应无效,且必须保持一定时间以使振荡器重启动并稳定工作空闲和掉电模式外部引脚状态•程序存储器的加密AT89C51可使用对芯片上的3个加密位LB
1、LB
2、LB3进行编程(P)或不编程(U)来得到如下表所示的功能加密位保护功能表:加密位保护功能当加密位LB1被编程时,在复位期间,EA端的逻辑电平被采样并锁存,如果单片机上电后一直没有复位,则锁存起的初始值是一个随机数,且这个随机数会一直保存到真正复位为止为使单片机能正常工作,被锁存的EA电平值必须与该引脚当前的逻辑电平一致此外,加密位只能通过整片擦除的方法清除•Flash闪速存储器的编程:AT89C51单片机部有4k字节的FlashPEROM这个Flash存储阵列出厂时已处于擦除状态(即所有存储单元的容均为FFH)用户随时可对其进行编程编程接口可接收高电压(+12V)或低电压(Vcc)的允许编程信号低电压编程模式适合于用户在线编程系统,而高电压编程模式可与通用EPROM编程器兼容AT89C51单片机中,有些属于低电压编程方式,而有些则是高电压编程方式,用户可从芯片上的型号和读取芯片的名字节获得该信息,见下表AT89C51的程序存储器阵列是采用字节写入方式编程的,每次写入一个字节,要对整个芯片的PEROM程序存储器写入一个非空字节,必须使用片擦除的方式将整个存储器的容清除•编程方法编程前,须按表6和图6所示设置好地址、数据与控制信号编程单元的地址加在P1口和P2口的P
2.0-P
2.3(11位地址围为OOOOH-OFFFH)数据从P0口输入引脚P
2.
6、P
2.7和P
3.
6、P
3.7的电平设置见表6PSEN为低电平,RST保持高电平EA/Vpp引脚是编程电源的输入端,按要求加上编程电压,ALE/PROG引脚输入编程脉冲(负脉冲)编程时,可采用4-20MHZ的时钟振荡器,AT89C51编程方法如下在地址线上加上要编程单元的地址信号在数据线上加上要写入的数据字节激活相应的控制信号在高电压编程方式时,将EA/Vpp端加上+12V编程电压每对FIash存储阵列写入一个字节或每写入一个程序加密位,加上一个ALE/PROG编程脉冲改变编程单元的地址和写入的数据,重复1一5步骤,直到全部文件编程结束每个字节写入周期是自身定时的,通常约为
1.5mso•数据查询AT89C51单片机用数据查询方式来检测一个写周期是否结束,在一个写周期中,如需读取最后写入的那个字节,则读出的数据的最高位(P
0.7)是原来写入字节最高位的反码写周期完成后,有效的数据就会出现在所有输出端上,此时,可进入下一个字节的写周期,写周期开始后,可在任意时刻进行数据查询•Ready/Busy:字节编程的进度可通过RDY/BSY输出信号监测,编程期间,ALE变为高电平后P
3.4(RDY/BSY)端电平被拉低,表示正在编程状态(忙状态)编程完成后,P
3.4变为高电平表示准备就绪状态•程序校验如果加密位LB
1、LB2没有进行编程,则代码数据可通过地址和数据线读回原编写的数据,采用下图的电路,程序存储器的地址由P1和P2口的P
2.0-P
2.3输入,数据由P0口读出,P
2.
6、P
2.7和P
3.
6、P
3.7的控制信号见表,PSEN保持低电平,ALE、EA和RST保持高电平校验时,P0口须接上10k左右的上拉电阻Flash存储器编程真值表注片擦除操作时要求PROG脉冲宽度为10ms编程电路+5VAT89C51校验电路SEEFLASHPROGRAMMINGMODESTABLE3-24MHzP1A8•A11P
2.0•P
2.3POADDR.—OOOOH/OFFFHP
2.6P
2.7P
3.6P
3.7XIAL2+5VAT89C51PGMDATA—►USE10KPULLUPSALEEAXIAL1GNDRSTPSEN•AT89C51的极限工作参数极限参数工作温度III-55Cto+125°C储藏温度ill-65°Cto+150°C任一脚对地电压-
1.OVto+
7.OV最高工作电压
6.6V直流输出电流
15.0mA指导教师评语:指导教师签字:年月日PortPinAlternateFunctionsP
3.0RXDserialinputportP
3.1TXDserialoutputportP
3.2INTOexternalinterrupt0P
3.3INT1externalinterrupt1P
3.4TOtimer0externalinputP
3.5T1timer1externalinputP
3.6WRexternaldatamemorywritestrobeP
3.7RDexternaldatamemoryreadstrobeModeProgramMemoryALEPSENPORTOPORT1PORT2PORT3IdleInternal11DataDataDataDataIdleExternal11FloatDataAddressDataPower-downInternal00DataDataDataDataPower-downExternal00FloatDataDataDataProgramLockBitsProtectionTypeLB1LB2LB31UUUNoprogramlockfeatures2PUUMOVCinstructionsexecutedfromexternalprogrammemoryaredisabledfromfetchingcodebytesfrominternalmemoryEAissampledandlatchedonresetandfurtherprogrammingoftheFlashisdisabled3PPuSameasmode
2.alsoverifyisdisabled4PPpSameasmode3alsoexternalexecutionisdisabledVpp=12VVPP=5VTop-SideMarkAT89C51xxxxyywwAT89C51xxxx-5yywwSignature030H=1EH031H=51H032H=FFH030H=1EH031H=51H032H=05HModeRSTPSENALE/PROGEA/VppP
2.6P
2.7P
3.6P
3.7WriteCodeDataHLH/12VLHHHReadCodeDataHLHHLLHHWriteLockBit-1HLH/12VHHHHBit-2HLH/12VHHLLBit-3HLH/12VHLHLChipEraseHLH/12VHLLLReadSignatureByteHLHHLLLLn口口口口口口/9inpcoCMT-Go7o398389371036113512341333143215311630%6oCMco十LO929妒”T-CMCMCMCMCMCMCMCMCM:IIREGISTERACCSTACKPOINTERPORT1LATCHPORT3LATCHTtOSOPORT1DRIVERSPORT3DRIVERS端口引脚第二功能P
3.0RXD(串行输入口)P
3.1TXD(串行输出口)P
3.2INTO(外中断0)P
3.3INT1(外中断1)P
3.4T0(定时/计数器0外部输入)P
3.5T1(定时/计数器1外部输入)P
3.6WR(外部数据存储器写选通)P
3.7RD(外部数据存储器读选通)模式程序存储区ALBPSEN0P1P2P3空闲模式内部11数据数据数据数据空闲模式外部11浮空数据地址数据掉电模式内部00数据数据数据数据掉电模式外部00浮空数据数据数据程序加密位保护类型LB1LB2LB31UUU没有程序保护功能2PUU禁止从外部程序存储器中执行MOVC指令读取内部程序存储器的内容3PPU除上表功能,还禁止程序校验4PPP除以上功能外,同时禁止外部执行VPP=12vVPP=5V芯片顶面标识AT89C51XXXXyywwAT89C51xxxx-5yyww签名字节030H=1EH030H=51H032H=FFH030H=1EH.030H=51H032H=05H方式RSTPSENALE/PROCEAA/ppP
2.6P
2.7P
3.6P3J与代码数据HLH/12VLHHH读代码数据HLHHLLHH与加密位Bit-1HLH/12VHHHHBit-2HLH/12VHHLLBit-3HLH/12VHLHL片摞除HLH/12VHLLL读签名字节HLHHLLLL。