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FEATURES腕16-12MSPS CMOS,16-Bit Sig ma-Delta ADC
1.2MSPS OutputWord Rate32/16X OversamplingRatio Sigmar-Delta ADCAD7723Low-Pass andBand-Pass Digital FilterLinear PhaseOn-Chip25V VoltageReference FUNCTIONALBLOCK DIAGRAMStandby ModeFlexibleParallel orSerial InterfaceCrystal Oscillator
2.5V REF2AVDD AD7723REFERENCE REF1Single+5V SupplyAGNDVIN+CID DVDDVIN-MODULATOR FI%R DGNDUNIXTALCLOCKHALF_PWR XTAL_OFFSTBY XTALCLKINMODE1DGND/DB15MODE2DGND/DB14SYNC SCR/DB13DVDD/CS SLDR/DB12CFMT/RD CONTROLLOGICSLP/DB11DGND/DRDY TSI/DB10DGND/DB0FSO/DB9DGND/DGND/DGND/DOE/SFMT/FSIZSCO/SDO/DB1DB2DB3DB4DB5DB6DB7DB8GENERAL DESCRIPTIONThe partprovides anon-chip
2.5reference.Alternatively,an externalThe A D7723is a complete16-bit,sigma-delta ADC.The partoperates fromreference can be useda+53supply.The analog input is continuously sampled,eliminating theApower-down modereduces theidle powerconsumption to200pW.need for an externalsample-and-hold.The modulatoroutput isprocessedThe AD7723is availablein a44-lead PQFPpackage and is specifiedoverby afinite impulseresponse FIRdigital filter:The on-chip filteringtheindustrial tcmperature rangefrom-40℃to+85℃.combined with a high oversampling ratioreduces the external antialiasrequirements to firstorder inmost casesThe digital filter frequencyT woinput modes are provided,allowing bothunipolar andbipolar inputresponsecan beprogram medto beeither low pass or band pass.ranges.The A D7723provides16-bit performancefor inputband widthsup to460kHzat anoutput word rate upto
1.2M Hz.The samplerate,filter cornerfrequenciesand output wordrateare setby thecrystal oscillatororexternal dockfrequency.Data can be readfrom the device ineither serial or parallelformat Astereomode allowsdata fromtwo devicesto share a singleserial dataline.All interface modes offereasy,high speedconnections tomoderndigital signalprocessorsREV.0Information furnishedby Analog Devices isbelieved to be accurateand reliable.One TechnologyWay,P.
0.Box9106,Norwood,MA02062-9106,U.S.A.Tel:However,no responsibilityis assumed byAnalog Devicesfor itsuse,nor for any781/329-4700W orldWide WebSite:w w.analog,co minfringements ofpatents orother rightsof thirdparties whichmay resultfrom itsFax:781/326-8703©Analog Devices,Inc.,1998use.No licenseis grantedby implicationor otherwiseunder anypatent orpatentrights ofAnalogDevices.PARALLEL MODEPIN FUNCTION DESCRIPTIONSM nemonic PinNo.DescriptionDVDD/CS30Chip SelectLogic InputCFMT/RD4Read Logic Input Usedin conjunctionwith CSto readdata from the parallelbus.The output databus isenabled when the rising edge of CL KI N senses a logic low level on RDif CSis alsolow.WhenR D is sensedhigh,the output data bits,DB15-DBO will be high impedance.D G N D/D R D Y5Data ReadyLogic OutputA falling edge indicatesa new outputword is availableto be read fromthe output data register DR D Y will returnhigh uponcompletion of a readoperation.If aread operationdoesnot occurbetween outputupdates,DR D Ywillpulse high for twoCL KI N cyclesbefore thenextoutput updateDR DY alsoindicates whenconversion resultsare availableafter aSY NC sequence.DGND/DB1531Data OutputBit,MSBDGND/DB1432Data OutputBitData OutputBitSCR/DB1333SLDR/DB1234Data OutputBitSLP/DB1135Data OutputBitTSI/DB1O36Data OutputBit37FSO/IB9Data OutputBitSDO/DB838Data OutputBit40Data OutputBitSCO/DB741Data OutputBitFSI/DB642Data OutputBitSFMT/DB5D0E/DB443Data OutputBit44Data OutputBitD G N D/DB31Data OutputBitD G N D/DB2Data OutputBitDGND/DB12DGND/DBO3Data OutputBit,LSB.SERIAL MODEPIN FUNCTION DESCRIPTIONSM nemonic PinNo.DescriptionCF MT/RD4Serial ClockFormat LogicInput The clock format pin selectswhether the serial data,SD0,is valid on the risingor falling edge of the serial clock,SCO.When CF M T is logic low,serial data is valid on the falling edge ofthe serialclock,SCO.If C FM Tislogic high,SD0is validon the rising edge of SCO.DOE/DB443Data Output Enable LogicInput.The DOE pin controls the three-state output buffer of the S D0pin.The activestate of D0E isdetermined bythe logic level on the TSIpin.When the10E logic level equalsthe level on theTSIpin the serial dataoutput,SD0,is active.Otherwise SD0will behigh impedance.SD0can bethree-stateafter a serial data transmission byconnecting DOEto FSO.In normaloperations,TSI and DOE should be tied low.SFMT/DB542Serial DataFormat LogicInput Thelogic levelon theSF M T pinselects theformat of the FS0signal forSerialMode
1.A logic low makesthe FSOoutput apulse,one SCOcycle wideat the beginning of a serial data transmissioaWithSF M T set to atogic high,the FS0signal is a framepulse that is activelow for the durationof the16-bittrans missioaFor Serial Modes2and3,SF M T should be tiedhigh.FSI/DB641Frame Synchronization LogicInput The FSIinput is used to synchronize the AD7723serial output dataregistertoan externedsource and to allowmore than one AD7723,operated from a com mon master clock,to simultaneously sampleits analog input andupdate its output registerSCO/DB740Serial ClockOutputSD0/DB838Serial DataOutput.The serial dataisshifted outMSB first,synchronous with the SCO.SerialM o de1datatransmissions last32SC0cycles Afterthe LSBis output,trailing zerosare outputfor theremaining16SCO cyclesSerial Modes2and3data transmissionslast16SCO cyclesFS0/DB937Frame Sync Output FSOindicates the beginning of a wordtrans missionon the SD0pin.Depending on the logiclevelof theSFM Tpin,the FSOsignal is either apositive pulseapproxi matelyone SCOperiod wide,or airame pulsewhichis activelow for the durationof the16-data bittransmission.TSI/DB1O36Ti meSlot LogicInput Thelogiclevelon TSIsets the active stateof the DOEpin.With TSIset logic high,DOEwill enabletheSD0output bufferwhen itis a logic high,and viceversa TSIis usedwhen two A D7723sareconnectedto the same serial data bus.When thisfunction is not needed,TSI andDOE should be tiedlow.SLP/DB1135Serial ModeLow Pass/Band Pass Filter Select Input With SLP set logic high,the low-pass filter response is selected.A logic low selectsband pass.SLDR/DB1234Serial ModeLow/High Output Data Rate SelectInput WithSLD Rsetlogic high,the lowdata rate is selectedAlogic low selects thehigh datarata Thehigh data rate corresponds to data at the output of the fourthdeci mationfilterDeci mate by
16.The lowdata ratecorrespondstodataat the output of thefifth decimation filterDecimate by
32.SCR/DB1333Serial ClockRateSelectInputWithSCR setlogic low,the serialclock outputfrequency,SC0,is equal to theCL KI N frequency.A logic high setsit equal to one-half the CL KI Nfrequency.DV/CS30Tie to DV DDD D32DGND/DB14Tie to DGND.DGND/DB1531Tie to DGND.DGND/DRDY5Tie toDGND.DGND/DBO3Tie toDGND.DGND/DB12Tie toDGND.DGND/DB21Tie toDGND.D GN D/DB344Tie toDGND.TERMINOLOGY ofgain for the differentialsignal to the gainfor thecom mon-mode signalSignal-to-Noise RatioSNRUnipolax OffsetErrorSNR is the measuredsignal-tern oiseratio at the output of the ADC.TheU nipolaroffset erroris thedeviation of the first code transition
10...signal is the rmsmagnitude of the fundamentalN oiseis the rms sum of000to
10...001from theideal differentialvoltage VIN+-VIN-+all of the nonfundamentalsignals upto halfthe output data rateF/2,
0.5LSB when operating in the unipolarmode.excluding de.The A D C is evaluatedby applyinga lownoises lowdistortionBipolar OffsetErrorsine wavesignal to the inputpins.By generatinga FastFourier TransformThis is thedeviation of the midscaletransition code
111...11to
000...FFT plot,the SNRdata canthen beobtained from the outputspectru m.00from theideal differentialvoltage VIN+-VI N--Q5LSB whenTotalHar monicDistortion T H Doperatingin the bipolar mode.T HD is the ratio of the rms sumof theharmonics to therms value ofGain Errorthe fundamentaLTHDisdefined as:T hefirstcodetransition shouldoccur atan analogvalue1/2LSB above-full scaleThe lasttransition shouldoccur for an analogvalue11/22y2y22V2Q”y+++V5+6乙LSB belowthe nominalfull scaleGain erroristhedeviation of the actualVidifference between firstand last code transitionsand theidealwhere Visthermsamplitude of the differencebetween firstand lastcode transitions.THD=20logfundamental and V V©V VandVare therms》中56amplitudes of the secondthrough sixthharmonics.The THDis also derivedfrom theFFT plotof the ADC outputspectru m.Spurious FreeDyna micRange SFD RDefined as the difference,in dB,between thepeak spuriousor harmoniccomponentin the ADC outputspectrum upto Fo/2and excludingde andthermsvalueof thefundamentaL Normally,the valueof thisspecificationwill bedetermined bythe largestharmonic in the outputspectrum of theFFT.For input signals whosesecond harm onics occurin thestop bandregionof the digital filtei;the spurin the noise floorlimits theSFDR.Passband RippleThe frequency response variation of the AD7723in thedefined passbandfrequencyrange.Passband FrequencyThefrequency upto which the frequencyresponsevariationis within thepassband ripplespecification.Cutoff FrequencyThefrequency belowwhich the AD7723sfrequency responsewill nothavemore than3dB of attenuationStopband FrequencyThefrequency abovewhichthe AD7723sfrequency responsewill bewithinits stopband attenuation.Stopband AttenuationThe AD7723sfrequency responsewill nothave less than90dB of attenuationin the stated frequencybandIntegral NonlinearityThisisthe maxi mu mdeviation of any codefromastraight linepassingthrough the end pointsof thetransfer functionThe endpointsof thetransferfunction areminus fullscale,a point
0.5LSB belowthe firstcodetransition
100...00to
100...01in bipolar mode,
000...00to
000...01in unipolarmode andplus fullseal®a point
0.5LSB abovethelastcodetransition
011...10to Oil...11in bipolarmode,
111...10to
111...11in unipolarmode.The erroris expressedin LSBs.Differential NonlinearityThis isthedifferencebetween the measuredand theideal1LSB changebetweentwo adjacentcodes in the ADC.Co mmon-Mode RejectionRatioThe abilityof adevice toreject theeffect ofa voltageapplied tobothinput terminalssimultaneously oftenthrough variationofaground一level-is specifiedas a com mon-mode rejectionratio.C M R RistheratioTypical PerformanceCharacteristics-AD7723AVDD=DVDD=5V;T=+25DC;CLKIN=
19.2MHz;External+25V Reference,unless otherwise notedA106110SIGNAL FREQUENCY=98kHzSIGNAL FREQUENCY=98kHz…MEASUREMENT BANDWIDTH=300kHz104MEASUREMENTBANDWIDTH=460kHz1003RD10290100THD8098SFDR70SNR6094THD9250SNR9040_28-23-18-13-8-3288-50-250255075100ANALOGINPUTLEVEL-dBTEMPERATURE-[!CFigure
9.SNR,THD and SFDR vs.Analog InputLevelFigure
12.SNR andTHD vs.Te mperatureOutput DataRelativeto Full Scale Output Data Rate=
1.2MHzRate=600kHz110106SIGNAL FREQUENCY=98kHzMEASUREMENT BANDWIDTH=300kHz100104SFDR10290100THDTHD988096SFDRINPUTSIGNAL=10kHz7094MEASUREMENTBANDWIDTH=
0.383X OWRSNR9260908850SNR864084-28-23-18-13-8100500100015002150-32ANALOGINPUT LEVEL-dB OUTPUT WORD RATE-kHzFigure
10.SNR,T11D and SFDR vs.Analog InputLevel Figure
13.SNR,T11D andSFDR vs.Sampling FrequencyDeci mate byRelative toFullScaleOutput Data Rate=600kHz16102115SIGNAL FREQUENCY=98kHzINPUT SIGNAL=10kHzMEASUREMENTBANDWIDTH=460kHz100MEASUREMENT BANDWIDTH=
0.5ZOWR3RD98110962ND SFDR94THD105929010088THDSNR869584SNR-50-250255075100TEMPERATURE一DC9050150300450600750900OUTPUTWORD RATE-kHzFigure
11.SNR andTHD vs.Te mperatureOutput DataFigure
14.SNR,THD andSFDR vs.Sampling FrequencyDeci matebyRate=
1.2MHz
3250001.0067108864SAMPLES TAKEN
0.80DIFFERENTIAL MODE
1.0067108864SAMPLES TAKEN2000V|N+=V|N-18008192SAMPLES TAKEN
0.80DIFFERENTIAL MODE
16000.
6014000.
4012000.
2010000.00800-
0.20600-
0.40400-
0.60200-
0.8003270032702327043270632708327103271232713-
1.00016384327684915265535CODE CODEFigure
15.Histogram ofOutput Codeswith DCInput Output Data RateFigure
18.Differential NonlinearityOutput Data=
1.2MHz Rate=600kHz450081”SAMPLES TAKEN
0.
6040000.
4035000.
2030000.002500-
0.202000-
0.401500-
0.601000-
0.80500-
1.00016384327684915265535CODE03270332704327053270632707327083270932710Figure
19.Integral NonlinearityOutput DataCODERate=
1.2MHzFigure
16.Histogram ofOutput Codeswith DCInput OutputData Rate=600kHz
1.
001.0067108864SAMPLES TAKEN67108864SAMPLES TAKEN
0.80DIFFERENTIAL MODE
0.80DIFFERENTIAL MODE
0.
600.
600.
400.
400.
200.
200.
000.00-
0.20-
0.20-
0.40-
0.40-
0.60-
0.60-
0.80-
0.80-
1.00-
1.00016384327680163843276849152655354915265535CODECODEFigure
17.Differential NonlinearityOutputData Rate=
1.2MHz Figure
20.Integral NonlinearityOutputDataRate=600kHz225m,so thatmost of the noise energy isshifted outof the band of interestFigure24b.200AI DDHALF_POWER=0175The digital filter thatfollows the modulator removesthe largeout-of^bandquantization noise,Figure24c whilealso reducingthe data rate from150fdKiN at the input of the filter tofcLKix/32or fcLKiN/16atthe output125of thefilter;depending on thestateon theMODE1/2pins in parallelinterface modeorthepin SLD Rin serialinterfacemode.The A D7723output100AIDD HALF_POWER=1data rateis aEttle overtwice the signal bcindwidth,which gueirantees75-DO thatthere isno loss of datain thesignal band.50Digital filteringhas certain advantages overanalog filtering.Firstly,25since digital filtering occursafter the A/D conversion,it canre movenoiseinjected during the conversionprocess Analogfiltering cannot00510152025remove noiseinjected duringconversion Secondly,the digital filterCLOCK FREQUENCY-MHzcombines lowpass bandripple with a steeproll-offi whilealso maintainingFigure
21.Power Consumption vs.CLKIN Frequencyquantizationa linearphase response.noise,a high order modulatoris employedto shapethenoisespectruSNR=-
86.19dBSNRD=-
85.9dB-25THD=-
96.42dBQUANTIZATIONNOISESFDR=-
99.61dB2ND HARMONIC=-
100.98dBCLKIN/23RD HARMONIC=-
99.61dB-50BAND OFINTERESTIN=100kHzaMEASURED BW=460kHz-75-100NOISE SHAPING,CLKIN/2-125BAND OFINTERESTb-1500E+0100E+3200E+3300E+3400E+3500E+3600E+3FREQUENCY-HzDIGITAL FILTERCUTOFFFREQUENCYFigure
22.16K PointFFT OutputDataRate=
1.2MHzo fCLKIN/2BAND OFINTERESTcSNR=-
89.91dB-20SNRD=-
89.7dBTHD=-
101.16dB reducedFigure24a.To furtherreduce theSFDR=-
102.1dBTO2ND HARMONIC=-
102.1dBFigure
24.Sigma-Delta ADC3RD HARMONIC=-
110.3dB_60AIN=50kHzThe A D7723employs fouror fiveFinite ImpulseResponse FIRfiltersMEASURED BW=300kHzin scriesEach individualfilte/soutputdatarateis half that of the-80filtef sinput datarate.When datais fedto the interface from the outputof the fourthfilter;the outputdata mtp mT-100CLKIN/16and the resulting OverSampling RatioOSR of the-120converter is
16.Data fedto theinterface from theoutputofthefifthfilter resultsin anoutputdatarate offcLKiN/32and acorresponding-140OSR for the converterof
32.When anOutputDataRate0D Rof fci.Kix/32isselected,the digital filterresponsecan beset toeither low-pass-1600E+050E+3100E+3150E+3200E+3250E+3300E+3orband-pass.The bandpassresponse isuseful when the input signal isFREQUENCY-Hzband limited since theresultingoutputdatarateishalfthatrequiredFigure
23.16K PointFFT OutputDataRate=600kHz toconvert theband when the lowpass operatingmode is used Toillustratethe operationof thismo de,consider aban d-U mitedsignal as shown inCIRCUITDESCRIPTION Figure25a Thissignal band can becorrectly convertedby selectingtheThe A D7723ADC employsa sigma-delta conversiontechnique toconvert the lowpass0DR=fcLKix/16mode,as shown in Figure25b.Note thattheanalog inputinto anequivalent digitalword Themodulator samplestheoutputdatarateis alittle overtwice themaximuin frequencyin theinputwaveform andoutputs anequivalent digitalword atthe inputclockfrequency band Alternatively theband-pass modecan beselected as shownfrequency,fin Figure25c Theband-pass filterremoves unwantedsignals from de toCI.KIN-just belowfcLKiN/
64.Rather thanoutputting dataat fcLKix/16,the outputDue to thehighoversamplingrate,which spreadsthe quantizationnoiseof theband-pass filter is sampledat fci.KiN/
32.Thisfrom0to FCLKIN/Z thenoiseenergycontained in thebandofinterestiseffectively translatesthe wantedband to a maximum frequencyofalittleless thanfcLKiN/64as shown in Figure25d.Hakdng theoutputdataratereduces thework loadof anyfollowing signalprocessor and also allowsa lower serialclock rateto be used.BAND LIMITEDSIGNAL-100dBOdBfCLKIN/16aLOWPASS FILTERRESPONSEODROdBSAMPLE
0.
00.
51.0IMAGECLKINFigure26b.Low-Pass Filter Deci mateby32fCLKIN/16LOWPASS FILTER.OUTPUT DATARATE=fcLKIN/16bBAND-PASS FILTERRESPONSESAMPLEOdBOdBIMAGECLKIN/16BAND-PASS FILTER.-100dBcFREQUENCYSAMPLETRANSLATED ODROdBINPUTSIGNAL IMAGEfCLKIN/16LOW PASSFILTER.OUTPUT DATARATE=fcLKIN/
320.
00.
51.0d fCLKINFigure26c.Band-Pass FilterDeci mateby32Figure
25.Band-Pass OperationFigure27a shows the frequencyresponse ofthe digitalfilter inbothlow-pass andband-pass modes.Dueto the samplingnature ofthe converter;Thefrequencyresponse ofthe threedigitalfilter operating modesisthe pass-band responseis repeatedabout the input samplingfrequency,shown in Figures26a26b,and26c.fcLKiN andat integermultiples offciKiN.Out-of-band noiseor signalscoincidentwith anyofthefilterimages are aliased downto thepassband.However,due to the AD7723s highoversampling ratio,these bandsoccupyonly a small fractionofthespectru m,and mostbroadband noiseisattenuated byat least90dB.In addition,as shownin Figure27b,withOdB evena loworder filter;there issignificant attenuation atthe firsti magefrequency.This contrastswithanormal Nyquistrate converterwherea veryhighorderantialias filteris required to allowmost ofthe bandwidthto be used whileensuring sufficientattenuation atmultiples cffci.KiN.-100dBOdBo.黑
1.0CLKIN2fcLKIN3fcLKINo fcFigure27a.Digital FilterFrequency ResponseFigure26a.Low-PassFilterDeci mateby16OUTPUTDATA RATEANTIALIASFILTERRESPONSEREQUIREDOdB ATTENUATIONCLKIN/32fCLKINFigure27b.Frequency Responseof AntialiasFilterAPPLYING THEAD7723half^clock phase.Analog InputRangeThe A D7723has differentialinputs to provide common-mode0A AD7723g^se^ejection.In unipolarmode the analoginput range is0to+4/5500Vx£F2‘while inbipolarmodethe analoginput range is-REF2-The outputVIN+2pFcode istwos complementbinary inboth modeswith1LSB=61pV.The DBidealinput/output transfercharacteristics for the twomodes areshown2pFQAin Figure28below.In bothmodes theabsolute voltageon eachinput
500、must remainwithin thesupply rangeAG N D toAV.The bipolarmode VIN-ACD[QB GROUNDallowseither single-ended orcomplementary input signals.
①CLKIN OAB以
①Bwhile alsosettling to the requiredaccuracy bytheendof each
011...111source driving the analoginputs must be ableto sourcethis charge,
011...110Figure
30.Analog InputEquivalent CircuitDrivingthe Analog Inputs
000...010To interface thesignal source to the AD7723,at leastone op amp will
000...001generally berequired.Choice ofop ampwill becritical to achiexdng theooo...ooofull performanceofthe A D
7723.The op amp notonly hasto recoverfromin...inthe transientloads thatthe ADCimposes onit,but mustalso havegood
111...110distortion characteristicsand verylow input noise.Resistors inthesignal pathwill alsoadd to the overallthermal noise floor,necessitating
100...001the choice of lowvalue resistors
100...oooPlacing anRC filterbetween thedrive sourceand the ADC inputs,asshown-4/5XVREF2ov+4/5XVREF2-1LSBBIPOLARin Figure31,has anumber ofbeneficial fects:transients on the op amp曲0V+4/5XVRE^2+8/5ZVREF2-1LSBUNIPOLARoutputs aresignificantly reducedsince the external capacitornowsupplies theinstantaneous chargerequired when the samplingcapacitorsFigure
28.Bipolar UnipolarMode TransferFunctionare switched to the ADC inputpins and,input circuitnoise atthe sampleThe AD7723will acceptfull-scale inbandsignals,however;large scaleoutimages isnow significantlyattenuated resultingin improvedoveL allSNR.of bandsignals canoverload themodulator inputs.Figure29shows themaximThe externalresistor servesto isolatethe external capacitor fromtheu minput signallevel as a functionof frequency.A minimal single-poleADC output,thus improvingopampstability whilealso isolatingthe opRCantialias filtersetto fcLKiN/24will allowfull-scale input signalsam poutput from any remainingtransients on the capacitor.Byover theentire frequencyspectru m.experimenting withdifferent filtervalues,the optimuin performancecanbe achievedfor eachapplication.As aguideline,the RCtime constantR
2.200x Cshould beless than a quarteroftheclock periodto avoidnonlinear
2.100currents fromthe ADC inputs beingstored on theexter^nalcapacitor anddegrading distortion.This restrictionmeans thatthis filtercannot form
2.000the mainantialias filterfor the A IC.
1.
9001.800VIN+
1.700AD
77231.
6001.500VIN-VREF=
2.5V
1.400Figure
31.Input RCNetwork
1.
30000.
020.
040.
060.
080.
100.
120.
140.5With theunipolar inputmode selected,just oneopampis rbquiredto bufferINPUT SIGNALFREQUENCY RELATIVETO f LKINCsingle endedinput signalsHowever,driving the AD7723with complementaryFigure
29.Peak InputSignal Levelvs.Signal Frequencysignalsand with the bipolarinputrangeselected hassome distinctAnalog Inputadvantages:even orderharmonics inboth thedrive circuitsand the AD7723The analoginput ofthe AD7723uses aswitched capacitortechnique tosamplefront endare attenuated;and thepeak to peak input signal rangeon boththeinput,signal.For thepurpose ofdrivingthe A D7723,an equivalentinputs is halvedHalving theinputsignalrange allowssome op amps to becircuit ofthe analoginputsis shownin Figure
30.For eachhalf clockpowered fromthe same suppliesas the AD
7723.Although acomplementarycycle,two highlylinear samplingcapacitors areswitchedtoboth inputs,driver willrequire the use oftwo opamps perADC,it mayavoid theneedconverting theinputsignalinto anequivalent sampledcharge.A signalto generate additionalsupplies justfor theseopamps.Figures32and33show twosuch circuitsfor drivingthe A D
7723.Figure modulatosswitched capDAC REF
2.When usingthe internal reference32is intendedfor usewhen theinputsignal is biasedabout25V whilea1pF capacitoris requiredbetween REFIandAGND to decouple theFigure33is usedwhentheinputsignalis biasedabout ground.While bandgapnoise.If the internal referenceis required to biasexternalboth circuitsconvert theinputsignalinto acomplementary signal,the circuits,use an external precisionopamptobufferREFI.circuit inFigure33also levelshifts thesignalso that bothoutputsare biasedabout
2.5V.Suitable opamps includethe A D8047,AD8044,AD8041and itsdualCOMPARATORequivalent the A D
8042.The AD8047has lowerinputnoisethan the1V AD7723AD8041/42but hastobesupplied fioma+
7.5V/-25V supply.TheREFERENCEAD8041/AD8042will typicallydegradeBUFFERREF1SNR from90dB to88dB butcan bepowered fromthe samesingle+5V supplySWITCHED-CAPDAC REFERENCEDas the AD
7723.1F3k\
2.5VREFERENCE■FBREF
2220、SOURCERINAIN=D2V50\390\AD8047BIASEDABOUT
2.5VA1VIN+Figure
34.Reference CircuitBlock DiagramWhere gain error orgainerrordrift requirestheuse of an exteL nal220\reference,the reference buffer inFigure34can beturned offby grounding220pFthe REF1pin and theexternal reference can be applied directly topin
220、AD7723REF
2.The AD7723will acceptanexteLnalreference voltage between
1.2V to
3.15V.By applyinga3V rather thana
2.5V reference,S NR27七10k\A2VIN-is typicallyimproved byabout1dB.Where theoutput common-mode rangeAD8047oftheamplifier drivingthe inputsis restricted,the full-scale inputREF2220nF10nF signalspan can be reduced by applyinga lowerthan
2.5V refer^ence.For example,a
1.25V referencewould makethebipolarinput span±1V,REF1but woulddegrade SNR.GAIN=2X RFB/RSOURCE+凡卜In all cases,sincethe REF2voltage connects to theanalog modulator,aFigure
32.Single-Ended toDifferential InputCircuit for220nF and10nF capacitormust connectdirectly fromREF2to AG ND.TheBipolar ModeOperation AnalogInput Biased About+25V externalcapacitor providesthe chargerequired for the dynamicloadpresented attheREF2pin SeeFigure
35.一
220、SOURCER|NAIN=2V
50、
390、AD8047BIASED27\ABOUTA1VIN+GROUNDOAc lBALANCE2RBALANCEI4pF
①B
220、220\REF2220pFRBALANCE2220nF10nF4pF DAAD7723220\RREFI27\SWITCHED-CAP10k\A2VIN-DAC REFERENCEDAD8047REF2CLKIN
①A QB以QB20k\220nF10nFFigure
35.REF2Equivalent InputCircuitREF1TheAD780is idealto useas an externalreferencewith the AD
7723.GAIN=2X RFB/RIN+RSOURCE1FKBALANCE1BALANCE2
八、SOURCE〃“八FBFigure36shows asuggested connection diagram.Grounding Pin8on theIXREF2=RREF1XR|N+RsOURCE/RFBA I780selects the3V outputmode.Figure
33.Single-Ended toDifferential InputCircuit forBipolar ModeOperationAnalogInputBiasedAboutGround
2.5V+5V REF2Applying theReference1NC SELECT82IN NC7The referencecircuitry used inthe AD7723includes anon-chip
2.5V220nF10nF AD7723bandgap referenceandareferencebuffercircuit Theblock diagramof1F22nF3TEMPVOUT6the referencecircuit isshowninFigure34The internalreferencevoltage4GNDTRIM522F REF1AD780is connected to REFIthrough a3kQ resistorandisinternally bufferedNC=NO CONNECTtodrive theanalogFigure
36.External ReferenceCircuit ConnectionClockGeneration mondata bus.Serial modeis idealwhen itis required to mini mize theT heAD7723contains anoscillator circuitto allowa crystaloran external numb erof data interface linesconnectedto a hostprocessor.In eitherclock signal togenerate the master clock for the ADC.The connectiondiagra case,careful attentionto thesyste mconfiguration isrequiredtorealizem for use witha crystalisshowninFigure
37.Consult themanufacturer thehigh dy-namic rangeavailable withthe AD
7723.Consult therccom-srecom mendationfortheload capacitorsTo enablethe oscillatorcircuit mendationinthe Layout andGrounding section.The followingrecomon boardthe AD7723,XT AL_OFF should be tiedlow.mendations forparallel interfacingalso apply forthesystem designwhenusing the serial mode.Parallel InterfaceAD7723When usingthe AD7723,place abuffei/latch adjacentto theconverter toXTALCLKINisolate theconverter sdata linesfromanynoise whichmay beonthe data1M\bus.Even thoughthe AD7723has threestate outputs,useof an isolationlatchrepresents gooddesign practice.Figure38shows howthe parallelinterface ofthe AD7723can beconfiguredto interfacewiththesyste mdata busofamicroprocessor oraFigure
37.Crystal OscillatorConnectionmicrocontroller such as theM C68H C16or8XC
251.With CS and RD tiedpermanentlylow,thedataoutput bitsarealways activeWhen DRI Y goesWhen anexternal clock source isbeing used,the internaloscillatorhigh fortwo clockcycles,therising edge ofDR DY is used tolatch thecircuitcan bedisabled bytying XTAL_OFF high.A lowphase noiseclockconversion databefore anew conversion result isloaded into the outputshould beused togeneratethe ADC sampling clockbecause samplingclockdata registerThe fallingedge ofDR DY thensends anappropriate interruptjittereffectively modulatestheinputsignal andraises thenoisefloor.signal forinterface control.Alternatively,if buffersare usedinsteadThe samplingclock generatorshould be isolated fromnoisy digitalcircuits,of latches,the fallingedge ofDR DY providesthe necessaryinterruptgrounded andheavily decoupledtotheanalog ground plane.when anewoutputwordis available fromtheAD
7723.The samplingclock generatorshould bereferenced totheanalogground inasplit groundsystem.However,this isnot alwayspossible becauseofsystein constraints.In manyapplications,the samplingclock must be AD7723DSPderived froma higherfrequency multipurpose syste m clockthatis1674XX1637416DBO-15DO-15generated onthe digital ground plane.If theclocksignalis passedbetweenits originonadigitalground plane totheAD7723ontheanalog groundADDRDECODE ADDRplane,the groundnoise betweenthe twoplanes addsdirectly tothe clockandwill produceexcess jitterThe jittercan causedegradation intheDRDYOEsignal-tcrnoise ratioandalsoproduce unwantedharmonics.This can beRDremedied somewhatby transmittingthesampling signalasadifferential CSone,using eitherasmallRF transformerorahigh speeddifferential driverRDINTERRUPTanda receiversuchasPECL.In eithercase,the originalmaster systemclockshould begenerated froma lowphase noisecrystal oscillatorFigure
38.Parallel InterfaceConnectionSYSTEM SYNCHRONIZATIONTheSY NCinputprovides asynchronization functionforusein parallelor serial mode.SY NC allowsthe userto begingathering samplesof theanaloginput froma knownpoint intime.This allowsa systeinusingmultiple AD7723s,operated froma commonmaster clock,tobesynchronizedso thateach ADCsimul-taneously updatesits output registerIn asystem usingmultiple AD7723s,acommon signalto theirsync inputswillsynchronize theiroperation Ontherising edgeofSY NC,the digitalfiltersequencer isreset to zero.The filteris heldinareset stateuntila rising edge onCLKIN sensesSYNC low.ASYNC pulse,one CLKI N cyclelong,can be applied synchronoustothe fallingedgeof CL KI N.This way,onthe nextrising edgeof CLKIN,SY NC issensed low,thefilteris takenoutof itsreset stateand multiple partsbegin togather inputsamples.Following aSY NC,themodulatorand filterneed time to settlebeforedata can bereadfromtheAD
7723.DRDYgoes high followingasynchronization andit remainshigh untilvalid dataisavailableat theinterface.DATA INTERFACINGTheAD7723offers achoiceofserialorparallel data interface optionstomeet therequire mentsofavariety ofsystemconfigurations.Inparallel mode,multiple AD7723s caneasily beconfigured toshare acomAT^WQQ—G.DD=DVDD=+5v□5%;AGND=AGNDI=AGND2=DGND=0v;乙AU1I DrELzl1H J-vVklXLzLNuf=
19.2MHz;REF2二25V;TA二RIN to TMAX;unless otherwisenotedaKINB VersionParameterTest Conditions/Co mments Min M ax UnitsTyp.DYNAMIC SPECIFICATIONS2-3H ALF_P WR=0or1fcLKiN=10MHz WhenHALF-PW R=1Deci mateby32Bipolar ModeSignal to NoiseFullPower
2.5V Reference8790dB3V Reference
88.591dBHalf Power
86.589dBTotal HarmonicDistortion1-96-90dBSpurious FreeDyna micRange
12.5V Reference-92dB3V Reference-90dBU nipolarModeSi gnalto Noise87dBTotal HarmonicDistortion4-89dBSpurious FreeDynamic Range4-90dBBandpass FilterModeBipolar ModeSignalto Noise7679dBD ecimateby16Bipolar ModeSignalto Noise M easure me nt Bandwidth=
0.383x Fo
2.5V Reference8286dB3V Reference8387dBSignal toNoise MeasurementBandwidth=
0.5x F
7881.5dBoTotal HarmonicDistortion
12.5V Reference-88dB3V Reference-86dBSpurious FreeDynamic Range
42.5V Reference-90dB3V Reference-88dBU nipolarModeSignaltoNoise Measurement Bandwidth=
0.383x F84dBoSignal toNoiseMeasurement Bandwidth=
0.5x F81dB0Total HarmonicDistortion1-89dBDIGITAL FILTERRESPONSELow PassDeci mateby320kHz tofcLKiN/
83.5±
0.001dBfcLKi N/
66.9-3dBfTKIN/64-6dBfcLKI N/
51.9to fcLKI N/2Group Delay-90dB1293/2f KiNCL1293/fCL KIN,Settling Ti meLow PassDeci mateby160kHz to fcLKiN/
41.75±
0.001dBfciKi N/
33.45-3dBfcLKIN/32-6dBfcLKIN/
25.95to fcLKIN/2Group Delay-90dB54l/2fLKINC541/fcLKINSettling Ti meBand PassDeci mateby32fcLKiN/
51.90tofcLKiN/
41.75±
0.001dBfcLKiN/6295,fcLKiN/
33.34-3dBfciKI N/64,fcLKiN/32-6dB0kHz tofcLKir/
83.5,LKIN/
25.95tofcLKiN/2-90dBGroup Delay1293/2fci.KiN1293/fcLKlNSettling TimeOutput DataRate,FoD ecimateby32fcLKi N/32D ecimale by16fcLKIN/16ANALOG INPUTSFull-Scale InputSpan VIN+-VIN-Bipolar Mode±4/5x VREF2VU nipolarMode08/5x VREF2VSERIAL INTERFACEconnectiondiagram.Si neeaserial data trans mission framelasts32TheAD7723s serial datainterfacecan operatein threemodes,depending SCO cycles,two ADCs canshareasingle data line byalternating transonthe applicationrequirements.The timingdia-grams inFigures3,4mission oftheir16-bit outputdata ontoone SD0pin.and5show howtheAD7723may beused totrans mitits conversion resultsTable Ishows the control inputsrequiredtoselect eachserial mode,andDV ADJ723the digitalfilteroperatingmode.TheAD7723operates solelyintheDDMASTERmaster modeproviding threeserial dataoutput pinsfor transfer oftheSFMT SDOTOHOSTconversion resultsThe serialdata clockoutput,SCO,serialdataoutput,CFMT SCOPROCESSORSD0,and femesync output,FS0,are allsynchronous withCL KTN.FS TSIFSODGNDFSI DOE0iscontinuouslyoutput atthe conversionrate ofthe ADC.CLKINSerial datashifts outoftheS DOpin synchronouswith SCO.The FSOisFROMused toframe theoutputdatatrans missionto anexternal device.An outputCONTROLLOGICdata transmission iseither16or32SCO cyclesin durationrefer to TableI.Serial datashifts outoftheSD0pin,MSB first,LSB last,foraAD7723SLAVEduration of16SCO cyclesIn Serial Mode1,SD0outputs zerosfor theFSIDOElast16SCO cyclesofthe32-cycle datatransmission frame.DVDDCLKIN SDOTheclock formatpin,CF MT,selects theactive edgeof SCO.With CFSFMT SCOTSIFSOM Ttied logiclow,the serialinterface outputsFSO andSD0change stateonthe SCOrisingedgeand arevalidonthefallingedgeofSC
0.WithDGND CFMTCFMT set high,FS0andSD0change stateonthefalling SCOedge andarevalidonthe SC0risingedge.Figure
39.Serial Mode1Connection forTwo-ChannelM ultiplexedOperationT heFrame Sync Input,FSI,can beused iftheAD7723convex sionprocessmust besynchronized to anexternalsource.FSI allowsthe conversiondata The DataOutput Enablepin,DOE,controlstheSD0outputbufferWhenpresented tothe serialinterface tobe afiltered anddeci matedresult thelogiclevelon DOEmatches thestateofthe TSIpin,the SDOoutputderived froma knownpoint intime.A common frame sync signalcan bebuffer drives the serialdata line,othei^wise theoutputofthe bufferappliedto twoor moreAD7723stosynchronize themtoacommonmaster goeshigh impedance.The serialformat pin,SF MT,is sethigh tochooseclock.the framesync outputformat.Theclockformat pin,CFMT,is setlowso thatserialdatais madeavailable onSD0after therisingedgeofW henFSI isapplied forthefirsttime,the digitalfilter sequencerSC0andcan be latchedontheSCO fallingedge.counter isreset tozero,theAD7723interrupts thecurrent datatransmission,reloads theoutput shiftregister;resets SC0and transmitsThe Master device isselected bysetting TSItoalogiclowand connectingtheconversionresultSynchronization startsim mediatelyand theits FSOto DOE.The Slavedevice isselected withits TSIpin tiedhighfollowing conversionsare invalidwhile the digitalfiltersettles FSIand bothits FSIandDOEcontrolled fromthe MastersFSO.Since theFScan beapplied onceafter power-up,or itcan bea periodicsignal,0oftheMaster controlstheDOEinputofboth theMaster andSlave,onesynchronous toCL KI N,occurring every32CL KIN cycles.Subsequent FSIADCsSD0is activewhile theother ishigh impedanceFigure
40.Wheninputs appliedevery32C LKINcycles do not alterthe serialdata theM astertransmits itsconversionresultduringthefirst16SC0cyclestransmission anddo notreset thedigitalfiltersequencer counterFSI ofa datatrans missionframe,thelow levelonDOE sets the slavds SDisan optionalsignal;if synchronizationisnotrequired,FSI can be tied0highimpedance.Once theMaster completestransmitting itsconversionto alogiclowand theAD7723will generateFSO outputsdata,its FSOgoeshigh,triggers theSlavg sFSI tobegin itsdata trcinsmissionframe.In Serial Mode1,thecontrolinput,SF MT,canbeusedtoselect theformatfortheserialdatatransmissionrefer toFigure
3.FS0iseitherSince FS0pulses aregated bythe releaseof FSIgoing lowand the FSIa pulse,approxi matelyone SCOcycle induration,orasquare wavewith ofthe Slavedevice isheld highduring itsdatatransmission,the FSaperiod of32SCOcyclesWith alogiclowlevelon SF MT,FS0pulses0fromtheMasterdevicemustbeused forconnection tothe hostprocessor.highforone SCOcycle atthe beginning ofadatatransmissionframe.Witha logichigh levelonSF MT,FS0goes lowatthebeginningofa datatransmissionframe andreturns highafter16SCO cyclesNotethat in Serial Mode1,FSI canbeusedtosynchronizetheAD7723if SFMTis settoalogichigh.If SFMTis setlow,theFSIinput willhaveno effecton synchronization.In Serial Modes2and3,SFMT should be tiedhigh.TSI andDOE shouldbe tiedlowin thesemodes.The FS0isapulse,approximately oneSCOcycle induration,occurring atthebeginningoftheserialdatatransmissioaTwo-Channel MultiplexedOperationT woadditional serialinterface controlpins,DOE andTSI,are providedtoallow theserialdataoutputs oftwoAD7723s,to easilyshcire oneserialdatalinewhenoperatinginSerial Mode
1.Figure39shows theCLKINFSISCO13FSO MASTERFSI SLAVEl15DOEMASTERSLAVED15D14f16SDO MASTERl9DOtl6i D1DOtl5D15D14SDOSLAVE D1Figure
40.Serial Mode1Timing forTwo-Channel MultiplexedOperationSERIAL INTERFACETO DSPSLAPS=0the DSPbegins reading the16-bit wordafter the DSP hasInserial mode,theAD7723canbedirectly interfacedto severalindustry identifiedthe framesync signalratherthanthe DSPreadingtheword atstandarddigital signalprocessors Inallcases,theAD7723operates asthe sameinstant asthe framesync signalhas beenidentified,LRFS=themasterwiththe DSP operatingastheslave.The AD7723provides its0RFS isactive high.own serialclock SCOto transmitthedigitalword onthe SDOpin tothe TheAD7723canbeusedin Modes1,2or3when interfacedtothe ADSP-2106xDSP.TheAD7723also generatesthe framesynchronization signalthat SHARCDSP.synchronizes thetransferofthe16-bit wordfromtheAD7723tothe DSP.AD7723-to-DSP56002InterfaceDepending ontheserialmode used,SC0will havea frequencyequal toFigure42shows theAD7723-to-DSP56002interface.To inteLfacetheAD7723CLKIN orequal toCL KIN/
2.When SCOequals
19.2M Hz,theAD7723canto the DSP56002,theADCis operated inMode2whentheADCis operatedbe interfacedto AnalogDevice^ADSP-2106x SHARCDSP.With a
19.2MHzwith a
19.2MHz clock.The DSP56002is configured as follows:SYN=1master clockand SCOequaltoCLKIN/2,theAD7723canbeintei^faced withsynchronousmode,SC D1=0RFS isan input,GC K=0a continuoustheADSP_21xx familyof DSPs,theDSP56002and theT MS320C5x-
57.Whenserial clock isused,SC KD=0theserialclock isexternal,W L1theAD7723isusedintheHALFPWR mode,ie,CLKIN islessthan10M Hz,=L WLO=0transfers willbe16bits wide,FSL1=0,FSLO=1the framethentheAD7723canbeused withDSPs suchastheT MS320C20/C25and thesyncwillbeactive atthebeginningof each transfer.Alternatively,DSP56000/
1.theDSP56002canbeoperatedinasynchronous modeSYN=
0.AD7723-to-ADSP-21xx InterfaceInthis mode,theserialclockforthe receivesection isinput totheFigure41shows theinterface betweentheADSP-21xx and theAD
7723.TheSC0pin.This isaccomplished bysetting bitSC D0to0external RxAD7723isoperatedinMode2sothatSC0C LKIN/
2.For theA DSP_21xx,二clock.the bitsintheserial portcontrol registershouldbeset upas RFSR=1a framesync isneeded for eachtransfer,SLEN=1516-bit wordlengths,RFS W=0normal framingmode forreceive operations,INVRFS DSP56002AD7723=0active highRFS,IRFS=0external RFSand ISCLK=0externalSDR SDOserialclock.SC1FSOthe receivedata willbe latchedinto theDSP onthefallingclock edge,SCK SCOADSP-21xx AD7723sync occursforeachtransfer.DR SDORFSFSO TMS320C5X AD7723SCLK SCODR SDOFSRFSOFigure
41.AD7723-to-ADSP-2Ixx InterfaceCLKRSCOA D7723-to-SHARC InterfaceTheinterfacebetweentheAD7723andtheA DSP_2106x SHARCDSP istheFigure
43.AD7723-to-TMS320C5x InterfacesameasshowninFigure41but,theDSPis configuredas follows:SLENGROUNDING ANDLAYOUT=1516-bit wordtransfers,SEN DN=0the MSBofthe16-bit wordwillT heanalog and digital powersupplies totheA17723are independentbereceived bytheDSPfirst,ICL K=0an externedserialclockwilland separatelypinned outto minimize couplingbetween analogand digitalbeused,RFSR=0a framesync isrequired forevery wordtransfer,sections withinthe device.All theIRFS=0the receiveframesyncsignalisexternal,CKRE=0AD7723AG ND andDG ND pinsshouldbesoldered directly toagroundFigure
42.AD7723-to-DSP56002Interfaceplane tominimizeseries inductance.In addition,theacpath fromanyA D7723-to-T MS320C5x Interfacesupply pinor referencepin REF1and REF2through itsdecouplingFigure43showstheAD7723-to-T MS320C5x interface.For theT MS320C5x,capacitors toits associatedground mustbe madeas shortas possibleFSRand CLK Rare automaticallyconfiguredasinputs.The serialport Figure
44.To achievethe bestdecoupling placesurface mountcapacitorsis configuredas follows:FO=016-bit wordtransfers,FS M=1a frameas closeas possibletothedevice,ideally rightup againstthe devicepinsAllground planesmust notoverlap to avoid capacitivecoupling.TheAD7723s cEgitaland analogground planesmustbe connected atone placebya lowinductance path,preferably rightunder thedevice.Typically,this connectionwill eitherbea trace onthe PrintedCircuit Boardof
0.5cm widewhentheground planesare onthesamelayer;or
0.5cm wideminimum platedthrough holeswhentheground planesare ondifferentlayers.Any externallogic connectedtotheAD7723should usea groundplaneseparate fromtheAD7723s digitalground plane.These twodigitalground planesshould alsobe connectedat justone place.Separate powersupplies forAV andD Vare alsohighly desirable.DD DDThe digitalsupply pinDV Dshouldbepoweredfroma separateanalog supply,Dbut ifnecessary DV D mayshare itspower connectionTO A1八°,「D vDD.Refer tothe connectiondiagra mFigure
44.The ferritesare alsoreco mmended tofilter highfrequencysignals fromcorrupting theanalog powersupply.A minimu metch techniqueis generallybest forground planesas itgivesthe bestshielding.Noise canbe minimized bypaying attentionto thesystem layoutand preventingdifferent signalsfrom interferingwith eachother.High levelanalog signals shouldbeseparated fromlowlevelanalogsignals,and bothshouldbekept awayfrom digitalsignals Inwaveformsampling andreconstruction systemsthe samplingclock CL KINis asvulnerableto noiseas anyanalog signal.CLKIN shouldbeisolatedfromthe analoganddigitalsystems.Fast switchingsignals likeclocks shouldbeshielded withtheir associatedground toavoid radiatingnoise toothersections ofthe board,and clocksignalsshouldnever berouted neartheanalog inputsAvoid runningdigital linesunder thedevice asthese willcouplenoise ontothe die.The analoggroundplaneshouldbeallowed torununder theAD7723to shieldit fromnoise coupling.The powersupplylines totheAD7723should useas largeatraceas possiblepreferablya planetoprovidealowimpedance pathand reducethe effectsof glitchesonthe powersupply line.Avoid crossoverof digitaland analogsignals Traceson oppositesides oftheboard shouldrun atright anglesto eachother.This willreduce theeffectsof feedthroughthrough theboardREF210nF220nFAGND21FREF1AV DD110nFAGND1+5V AGND1MVDD10nF10F100nF100nF AGNDMVDD10nFAGNDAD7723ANALOGGROUNDPLANEAD7723DIGITAL n\/r»r»GROUNDPLANE uvDD10nF10F100nF10nFDGNDDGNDFigure
44.Reference andPower SupplyDecouplingOUTLINE DIMENSIONSDimensions shownin inchesand mm.44-Lead Plastic Quad Flatpack
0.
54813.
9250.
54613.
8750.
0962.
440.
39810.11MAX
0.
3909.
910.
0370.948°
0.
0250.
6433230.8°3422S-44SEATING PLANETOP VIEWPINSDOWN
44120.
0401.
021110.
0401.
020.
0320.
810.
0320.
810.
0330.
840.
0160.
410.
0832.
110.
0290.
740.
0120.
300.
0771.96B VersionParameterTest Conditions/Co mments MinTyp Max UnitsANALOG INPUTSContinuedAbsolute InputVoltage VIN+and/or VIN-AGND A VDD VInputSampling Capacitance2pFInput SamplingRatQ FCLKIN
19.2M HzCLOCKCLKIN DutyRatio4555%REFERENCEREFI OutputResistance3kCUsing InternalReferenceREF2Output Voltage
2.
392.
542.69VREF2Output VoltageDrift60ppm/℃Using ExternalReferenceREF2Input ImpedanceREFI=AGND4kCREF2External VoltageRange
1.
22.
53.15VSTATIC PERFORMANCEResolution16BitsDifferential NonlinearityG uaranteed Monotonic±
0.5±1LSBIntegral Nonlinearity±2LSBDC CMRR80dBOffset Error±20m VGainErrorb±
0.5%FSRLOGIC INPUTSExcluding CLKINVINH,Input HighVoltage
2.0VViNb Input Low Voltage
0.8VCLOCK INPUTCLKINVINH,Input HighVoltage
3.8VVINL,InputLowVoltage
0.4VALL LOGICINPUTSIm InputCurrent VIN=0V toDVDD±10MAC N,Input Capacitance10pFLOGIC OUTPUTSVoibOutput HighVoltage1IOUT1=200|1A
4.0VVOL,Output LowVoltage1IOUT1=
1.6m A
0.4VPOWER SUPPLIESAV
4.
755.25VDDIAVDD HALF_P WR=Logic Low5060m AHALF_PWR=Logic High2533m ADV
4.
755.25VDDIDVDI IIALF_PWR=Logic Low2535m AHALFP WR=Logic High1520m APowerConsumption6Standby Mode200仆NOTESIOperating temperaturerangeisas follows:B Version:-40℃to+85°C.2TypiCcd veduesfor SNRapplyforparts soldereddirectlytoa printedcircuit boardgroundplane.Dyna micspecifications applyfor inputsignal frequenciesfrom deto
0.0240x fci.KiN indeci mateby16mode andfromdeto
0.0120x fci.KiN indeci mateby32mode.When usingthe internalreference,TH DandSFDRspecifications applyonly toinput signalsabove10kHz witha10pF decouplingcapacitor betweenREF2andA GND
2.At frequenciesbelow10kHz,TII Ddegrades to84dB andSFD Rdegrades to86dB.°GainErrorexcludes ReferenceError.6CLKIN anddigital inputsstatic andequalto0or D V DD.Specifications subjectto changewithout notice.V\v-UV-TO VLJOTO;AUIMJ-AU1NU1-IAJINU-U V;1—IN乙MHZ;U-OU pr;OF Ml一DD DDCLK1N LTIMINGSPECIFICATIONSLogic Lowor HighFMT=Logic Lowor Hi toT^x unless otherwisenoted加;=TMINParameter Symbol MinTyp MaxUnitsC LKINFrequency
119.2M HzFCLKCLKINPeriod tK=1/fciK
0.0521那CL tlCLKINLow Pulsewidth
0.45x ti
0.55x tit2CLKIN HighPulsewidth
0.45x ti
0.55x tit3CLKIN RiseTime5nsCLKIN FallTime5nst5FSI Setup Time05nst6FSI HoldTime05nst7FSI High Time11t8tCLKCLKIN toSCO Delay2540nst9SCO Period2,SCR=12tio tCLKSCOPeriod2,SCR=01tio tCLKSCO Transition to FS0High Delay05nstilSCO TransitiontoFS0Low Delay05nstl2SCO Transitionto SDOValid Delay512nstl3SCOTransitionfrom FSI3tl460tCLK+t2tl5520SDO EnableDelay Time nsSDO Disable DelayTimetl6520nsDR DYHighTime22tl7tCLKConversion Time2Refer to Tables Iand II16/32tl8tcLKCLKIN toDR DYTransition3550tl9nsCLKIN toDATA Valid2035nst20CS/RDSetupTimetoCLKIN0nst21CS/RD HoldTime toCLKIN20t22nsData AccessTime2035nst23Bus RelinquishTimet242035nsSYNC InputPulse width1t25tcLKSYNC LowTime beforeCLKIN Rising0nst26DR DYHigh Delayafter RisingSYNC2535t27nsD RDYLow Delayafter SYNCLow2049t28tcLKNOTES*FS0pulses aregated bythe releaseof FSIgoing low.2Guaranteed bydesign.Frame Syncis initiatedonthefallingedgeof CLKIN.Specifications subjectto changewithout notice.OL
1.6mATOOUTPUT+
1.6VPINCL50pF,OH200AFigure
1.Load Circuitfor Timing Specifications
2.3VCLKIN
0.8VFSISCO10Figure2SerialModeTiming forClock Input,Frame Sync Input and Serial ClockOutput32CLKIN CYCLESCLKINFSISFMT=114SCOCFMT=011FSOSFMT=012FSOSFMT=113SDO D15D14D13D2D1DO D15D14Figure3SerialMode
1.Timing forFra meSync Input,Fra meSync Refer to TableOutput,Serial ClockOutput andSerial DataOutputI forControl Inputs,TSI=DOE32CLKIN CYCLESCLKINFSI14SCOCFMT=01112FSOSDO D2D1DO D15D14D13D12D11D5D4D3D2D1DO D15D14Figure
4.SerialMode
2.Timing forFra meSyncInput,Fra meSync Output,Serial ClockOutput andSerial DataOutput RefertoTableI forControlInputs,TSI=DOE16CLKINCYCLESCLKINFSI14SCOCFMT=011FSO13SDO D2D1DO D15D14D13D12D11D5D4D3D2D1DOD15D14Figure
5.SerialMode
3.Timing forFra meSyncInput,Fra meSyncOutput,Serial ClockOutput andSerial Data0utput RefertoTableI forControlInputs,TSI=DOETable LSerial InterfaceModel=0,Mode2=0Deci mationDigitalFilterSCO FrequencySCR OutputData ControlInputsSLDR SLPSCRSerial ModeRatio SLDRMode SLPRate132Low Pass110fCLKIN fcLKlN/32132Band Pass100fCLKIN fcLKIN/32232Low Pass111fcLKIN/2fcLKIN/32232Band Pass101fcLKTN/2fcLKIN/32316Low Pass010fCLKIN fcLKIN/16Table ILParallel InterfaceDi gitalFilterDecimation OutputControl InputsModeRatio DataRate M0DEI M0DE2Band Pass0132fcLKIN/32Low Pass1032fcLKIN/32Low Pass1116fcLKIN/16DOEl15SDOFigure
6.SerialModeTi mingfor DataOutputEnableandSerialData Outputl18CLKIN1917DRDY20DB0-DB15WORD N-1WORDN WORDN+1Figure7a Parallel Mode Read Ti ming,CSandRD TiedLogic LowCLKIN1819DRDY22RD/CS2224DB0-DB15VALID DATA23Figure7ParallelModeReadTiming,CS=RDb.28CLKIN26SYNC25DRDYFigure
0.3VDD-Q3V toAV+
0.3V-Q3V toAV+
1.14XTAL_OFFOscillator EnableInput Alogichighdisables thecrystal oscillatoramplifier toallow useofanexter^nal clocksource.Set lowwhen usinganexternalcrystal betweentheCLKINand XTALpins.M0DE1/28,7Mode ControlInputs.The M0D E1and M0D E2pins chooseeither parallelorserialdatainterfaceoperationand selectthe operatingmode forthedigitalfilter inparallel mode.RefertoTables Iand ILHALF_P WR15W hensethigh,the powerdissipation isreducedbyapproximately one-half anda maximumCLKIN frequencyof10M HzappliesSYNC29SynchronizationLogicInput Whenusing morethanoneAD7723,operated fromacommonmasterclock,SYNC allowseachADC tosimultaneouslysampleits analoginput andupdate itsoutputregisterA risingedge resetstheAD7723digitalfiltersequencer countertozero.When therisingedgeof CLKINsensesalogiclowon SYNC,the resetstateis releasedBecause thedigitalfilterand sequencerare completelyreset duringthis action,SY NC pulsescannotbe appliedcontinuously.STBY27Standby LogicInput AlogichighsetstheAD7723intothepower-down state.。