如何在ISE中更新老版本的IP核

如何在ISE中更新老版本的IP核在ISE中打开以前做的一个工程时，总是不停地提示INFO:sim:760-You canuse theCORE GeneratorIP upgradeflow toupgradethe selected IP Block_Memory_Generator v

3.1to amore recentversion.老版本是ISE

11.1中生成的，现在用

12.4了，推荐更新IP核于是摸索了一下，找到了下面的步骤

1.在导航窗口中选择IP核生成的文件一

2.在core generator中双击manager core,如图所示回ISE ProjectNavigator M.81d-D:\dul_ram\dul_ram,xise-[Design Summary]E FileEdit ViewProject SourceProcess ToolsWindow LayoutHelpIM aI d＜8＞R IE口*日例哈卢即区唔臼H＞匕/电1©•Desi gnS-Design OverviewParserMessa；目••••SummarySimulati o:Proj ectMgmtIEViewImplement atio:[口•••IOB PropertiesHierarchy口；J iM r11k J1，・•••司duLram QXilinx CORE Generator-D:\dul_ram\ipcore_dir\coregen.cs白“□xc3s400-4tql44o门File ProjectView Help日“0oo dulram dulram.v打国Q duLraminst-dulramdul_r.间就n tdJ ICORE GeneratorHelp View by FunctionViewbyNameName VersionAXI4田・卜一AutomotiveIndustrial国B BaselPE-k BasicElements田卜田CommunicationNetworking卜；田七DebugVerification DigitalrrSignalProcessingrRunningManage Cores+-k FPGAFeatures andDesign；匚0•Math Functions汽日密-上Processes:dul_raminst-dul_ram•®MemoriesStorage Elements匕田卜二E-7Standard BusInterfacesCORE Generator力Storage,NAS andSAN0•1Video在Manage CoresRegenerateImage Processing国Core View HDL FunctionalModelViewHDLInstantiation国Te...Search IPCatalog:CleaAll IPversions OnlyIP compatiblewith chosenProjectIPInstance NameCore NameVersi《dul_ram Block Memory Generator

3.1的的Design FilesL LibrariesConsolerrRelease

12.4-Xilinx CORE Generator CopyrightcrSearch ProjectIP:1995-2010Xilinxr Inc.All runtiiEemessages will berecords Welcome to Xilinx CORE Generator.Helpsystem initialized.Opening projectfile D:\dul_rairi\ipcore_dir\coregen.cgp.INFO:sim:760-You canuse theCOREGeneratorIP upgradeflow toupgrade theselectedIP31ock_Memory_Generatorv

3.1to amore recentversion.Project^1coregen,initialised fromfile D:\dul ram\ipcore dir\coregen.cgp,.Console ErrorsWarnings gFind inFiles ResultsTqqPIaciatgo

3.1to amore recentversion.Project,coregen’,initialised fromfileD:\dul_ram\ipcore_dir\coregen.cgp.Upgrade andregenerate allproject IPlatest versions,under currentprojectsettingsApplying current project options...Finished applyingcurrent project options.Applying currentprojectoptions...Finished applyingcurrentprojectoptions.Upgrading IPdul_ram toBlockMemoryGenerator version

4.3Launching upgradeviewer...Launched upgradeviewer.Initializing IP model...Finished initialisingIP model.Generating IP...WARNING:sim:89-A corenamed alreadyexists inthe output directory.Output productsfor thiscore maybe overwritten.Initializing IPmodel...WARNING:sim:602-The parameter，Port_B_Write_Rate，is disabledand cantbeset toany othervalue thanO.Its valuewillbereset from’50toits lastvalid valueO’.WARNING:sim:192-Xco Parameterchanged fromPort_B_Write_Rate,50toPort_B_Write_Rate,0during Recustomization.Finished initialisingIPmodel.XST:HDL CompilationXST:Design HierarchyAnalysisXST:HDL AnalysisXST:HDL SynthesisXST:Advanced HDLSynthesisXST:Low LevelSynthesisGenerating Implementationfiles.Generating ISEsymbol file...WARNING:coreuti1-WARNING:Default charsetGBK notsupported,usingISO-8859-1insteadGenerating NGCfile.Finished GenerationStage.Generating IP instantiation template...VHDL instantiationtemplate alreadypresent,so notregenerating.WARNING:coreutil-WARNING:Default charsetGBK notsupported,usingISO-8859-1insteadFinished generatingIPinstantiationtemplate.Generating metadata file...Finished generatingmetadatafile.Generating ISEfile...Finished ISEfile generation.Generating FLISTfile...Finished FLISTfile generation.Preparing outputdirectory...Finished preparingoutputdirectory.INFO:sim-Created backupdirectoryD:\dul_ram\ipcore_dir\tmp\backup_dul_ram\Moving files to outputdirectory...Finished movingfilestooutput directorySavedoptions forproject coregen’.。